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    • 1. 发明申请
    • X87 FUSED MULTIPLY-ADD INSTRUCTION
    • X87 FUSED MULTIPLY-ADD指令
    • US20080256162A1
    • 2008-10-16
    • US11781754
    • 2007-07-23
    • G. Glenn HenryTimothy A. ElliottTerry Parks
    • G. Glenn HenryTimothy A. ElliottTerry Parks
    • G06F7/38
    • G06F7/483G06F7/5443G06F7/78G06F9/30014G06F9/30145G06F9/30163
    • An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.
    • 公开了x86架构微处理器的指令集中的x87融合乘法(FMA)指令。 FMA指令将两个因子操作数隐含地指定为x87 FPU寄存器堆栈的前两个操作数,并将第三个加数操作数明确指定为第三个x87 FPU寄存器堆栈寄存器。 微处理器乘以前两个操作数,并将产品添加到第三个操作数以生成结果。 结果存储在第三个寄存器中,前两个操作数从堆栈中弹出。 在替代实施例中,第三操作数也被隐含地指定为存储在堆栈寄存器顶部下方的两个寄存器的寄存器中; 结果也存储在其中。 指令操作码值在x87操作码范围内。
    • 2. 发明授权
    • Method and apparatus for double operand load
    • 双操作数负载的方法和装置
    • US06253312B1
    • 2001-06-26
    • US09130910
    • 1998-08-07
    • Timothy A. ElliottG. Glenn HenryTerry Parks
    • Timothy A. ElliottG. Glenn HenryTerry Parks
    • G06F1500
    • G06F9/30043G06F9/3867
    • An apparatus and method are provided for concurrently loading single-precision operands into registers in a microprocessor floating point register file. The apparatus includes translation logic, data logic, and write back logic. The translation logic receives a load macro instruction prescribing an address, and decodes the load macro instruction into a double load micro instruction. The double load micro instruction directs the microprocessor to retrieve the two single-precision operands from the address and to load the two single-precision operands into the two floating point registers. The data logic, coupled to the translation logic, executes the double load micro instruction and retrieves the two single-precision operands from the address. The write back logic, coupled to the data logic, loads the two single-precision operands into the two floating point registers during a single write cycle.
    • 提供了一种装置和方法,用于将单精度操作数同时加载到微处理器浮点寄存器文件中的寄存器中。 该装置包括翻译逻辑,数据逻辑和回写逻辑。 翻译逻辑接收指定地址的加载宏指令,并将加载宏指令解码为双载微指令。 双载微指令指示微处理器从地址中检索两个单精度操作数,并将两个单精度操作数加载到两个浮点寄存器中。 耦合到转换逻辑的数据逻辑执行双重负载微指令,并从地址中检索两个单精度操作数。 耦合到数据逻辑的写回逻辑在单个写周期期间将两个单精度操作数加载到两个浮点寄存器中。
    • 3. 发明授权
    • X87 fused multiply-add instruction
    • X87融合乘法指令
    • US07917568B2
    • 2011-03-29
    • US11781754
    • 2007-07-23
    • G. Glenn HenryTimothy A. ElliottTerry Parks
    • G. Glenn HenryTimothy A. ElliottTerry Parks
    • G06F7/38
    • G06F7/483G06F7/5443G06F7/78G06F9/30014G06F9/30145G06F9/30163
    • An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top two operands of the x87 FPU register stack and explicitly specifies the third addend operand as a third x87 FPU register stack register. The microprocessor multiplies the first two operands and adds the product to the third operand to generate a result. The result is stored into the third register and the first two operands are popped off the stack. In an alternate embodiment, the third operand is also implicitly specified as being stored in the register that is two registers below the top of stack register; the result is also stored therein. The instruction opcode value is in the x87 opcode range.
    • 公开了x86架构微处理器的指令集中的x87融合乘法(FMA)指令。 FMA指令将两个因子操作数隐含地指定为x87 FPU寄存器堆栈的前两个操作数,并将第三个加数操作数明确指定为第三个x87 FPU寄存器堆栈寄存器。 微处理器乘以前两个操作数,并将产品添加到第三个操作数以生成结果。 结果存储在第三个寄存器中,前两个操作数从堆栈中弹出。 在替代实施例中,第三操作数也被隐含地指定为存储在堆栈寄存器顶部下面的两个寄存器的寄存器中; 结果也存储在其中。 指令操作码值在x87操作码范围内。
    • 5. 发明授权
    • Apparatus and method for generating a cryptographic key schedule in a microprocessor
    • 用于在微处理器中产生加密密钥调度的装置和方法
    • US07539876B2
    • 2009-05-26
    • US10826632
    • 2004-04-16
    • G. Glenn HenryThomas A. CrispinTimothy A. ElliottTerry Parks
    • G. Glenn HenryThomas A. CrispinTimothy A. ElliottTerry Parks
    • H04L9/06
    • G06F21/72G06F9/30007H04L9/0631H04L9/0637H04L9/12H04L2209/125H04L2209/24
    • An apparatus and method for performing cryptographic operations. In one embodiment, an apparatus is provided for performing cryptographic operations. The apparatus includes fetch logic, keygen logic, and execution logic. The fetch logic is disposed within a microprocessor and receives cryptographic instruction single atomic cryptographic instruction as part of an instruction flow executing on the microprocessor. The cryptographic instruction single atomic cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a provided cryptographic key be expanded into a corresponding key schedule for employment during execution of the one of the cryptographic operations. The keygen logic is disposed within the microprocessor and is operatively coupled to the single atomic cryptographic instruction. The keygen logic directs the microprocessor to expand the provided cryptographic key into the corresponding key schedule. The execution logic is coupled to the keygen logic. The execution logic is disposed within the microprocessor and expands the provided cryptographic key into the corresponding key schedule.
    • 一种用于执行密码操作的装置和方法。 在一个实施例中,提供了一种用于执行加密操作的装置。 该装置包括提取逻辑,密钥生成逻辑和执行逻辑。 提取逻辑设置在微处理器内,并接收作为在微处理器上执行的指令流的一部分的加密指令单原子加密指令。 加密指令单原子加密指令规定了一个加密操作,并且还规定所提供的加密密钥在执行该加密操作之一期间被扩展为对应的密钥调度表。 密钥生成器逻辑设置在微处理器内并且可操作地耦合到单原子加密指令。 密钥生成逻辑指示微处理器将提供的加密密钥扩展到相应的密钥调度表中。 执行逻辑与keygen逻辑耦合。 执行逻辑设置在微处理器内,并将所提供的加密密钥扩展到相应的密钥调度表中。
    • 8. 发明授权
    • Mechanism for clipping RGB value during integer transfer
    • 整数传输期间裁剪RGB值的机制
    • US06791564B1
    • 2004-09-14
    • US09565834
    • 2000-05-05
    • Timothy A. ElliottG. Glenn Henry
    • Timothy A. ElliottG. Glenn Henry
    • G09G502
    • G09G5/02
    • A mechanism for, and method of, clipping a red-green-blue (RGB) integer value to an n-bit maximum value and a processor incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a multiplexer having a first input that accepts n low-order bits of the RGB integer value and a select input that accepts at least one high-order bit of the RGB integer value and (2) an n-bit maximum value generator, coupled to a second input of the multiplexer, that provides the n-bit maximum value to the second input, an output of the multiplexer providing the n low-order bits when the at least one high order bit has a zero value and providing the n-bit maximum value when the at least one high order bit has a nonzero value.
    • 一种将红 - 绿 - 蓝(RGB)整数值削减到n位最大值的机制和方法,以及包含该机构或方法的处理器。 在一个实施例中,该机制包括:(1)多路复用器,其具有接收RGB整数值的n个低阶位的第一输入和接受RGB整数值的至少一个高位的选择输入和(2 )n位最大值发生器,耦合到所述多路复用器的第二输入端,其向所述第二输入端提供所述n比特最大值,所述多路复用器的输出在所述至少一个高阶时提供所述n个低阶比特 位具有零值,并且当至少一个高位位具有非零值时提供n位最大值。
    • 9. 发明授权
    • Apparatus and method for improved floating point exchange
    • 改进浮点交换的装置和方法
    • US6014736A
    • 2000-01-11
    • US48524
    • 1998-03-26
    • Timothy A. ElliottG. Glenn HenryAlbert J. Loper, Jr.
    • Timothy A. ElliottG. Glenn HenryAlbert J. Loper, Jr.
    • G06F9/315G06F9/38
    • G06F9/30032G06F9/3836G06F9/3838G06F9/384G06F9/3857
    • A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.
    • 提供微处理器用于执行浮点交换微指令序列以将内容交换第一位置和第二位置。 微处理器包括接收浮点微指令的寄存器/控制逻辑,确定第一位置的内容取决于先前浮点微指令的分辨率,并提供指示依赖性的信号。 微处理器还具有互锁逻辑,在依赖性的情况下将新的目标位置转发到前一个浮点微指令。 微处理器还包括目标位置修改逻辑,其接收新的目标位置,并提供新的目标位置到先前的浮点微指令。 目标位置的修改允许浮点交换微指令序列执行无分辨率延迟。