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1. 发明授权

US4278943A Integration circuit 失效
标题翻译：集成电路
公开(公告)号：US4278943A
公开(公告)日：1981-07-14
申请号：US920343
申请日：1978-06-29
申请人： Eiji Masuda , Chikara Sato , Yasoji Suzuki
发明人： Eiji Masuda , Chikara Sato , Yasoji Suzuki
IPC分类号： G06G7/186 , H03K5/00
CPC分类号： G06G7/1865
摘要： An integration circuit comprises an operational amplifier with first and second input terminals and an output terminal, an integration capacitor connected between the first input terminal and the output terminal, an integration resistor connected at one end to the first input terminal, a switch connected at one end to the other end of said resistor, a voltage signal source to be integrated which is connected through the switch to the other end of the resistor, and a reference voltage signal source connected to the second input terminal. The integration circuit further comprises means which applies, at the same time as the switch is opened, a signal with the same potential as the signal derived from the reference voltage signal source to said other end of the resistor, thereby to prevent an output signal from being adversely affected by a parasitic capacitance of the switch.An integration method includes a first step for applying a voltage signal to be integrated to an input part of an integration circuit and a second step for stopping the application of the integration voltage signal to the input part, and further comprises a third step for applying a reference potential signal to the input part of the integration circuit at the same time as the voltage signal to be integrated stops.
摘要翻译：积分电路包括具有第一和第二输入端子的运算放大器和输出端子，连接在第一输入端子和输出端子之间的积分电容器，一端连接到第一输入端子的积分电阻器，结束到所述电阻器的另一端，要被集成的电压信号源，其通过开关连接到电阻器的另一端，以及参考电压信号源连接到第二输入端子。积分电路还包括在与开关同时打开具有与从参考电压信号源导出到电阻器的另一端的信号相同的电位的信号的装置，从而防止输出信号受到开关寄生电容的不利影响。积分方法包括：第一步骤，将要积分的电压信号施加到积分电路的输入部分;以及第二步骤，用于停止向输入部分施加积分电压信号，并且还包括第三步骤，与要积分的电压信号同时停止对积分电路的输入部分的参考电位信号。

2. 发明授权

US4364028A Integrating analog to digital converter having offset error compensation 失效
标题翻译：集成具有偏移误差补偿的模数转换器
公开(公告)号：US4364028A
公开(公告)日：1982-12-14
申请号：US255373
申请日：1981-04-20
申请人： Eiji Masuda , Yasoji Suzuki
发明人： Eiji Masuda , Yasoji Suzuki
IPC分类号： H03M1/52 , H03M1/00 , H03K13/02
CPC分类号： H03M1/0602 , H03M1/52
摘要： An integrating analog to digital converter having a switching circuit for selecting any one of an analog input voltage, a first reference voltage, or an analog ground voltage; an intermediate voltage selected by the switching circuit and the intermediate voltage generated by the intermediate voltage generating circuit; and a comparator for producing a signal to control the operation of the switching circuit and the voltage level produced by the intermediate voltage generating circuit according to the results of a comparison between the output signal from the integration circuit and a second reference voltage.
摘要翻译：一种具有用于选择模拟输入电压，第一参考电压或模拟地电压中的任何一个的开关电路的积分模数转换器; 由所述开关电路选择的中间电压和由所述中间电压产生电路产生的中间电压; 以及比较器，用于根据来自积分电路的输出信号和第二参考电压之间的比较结果产生用于控制开关电路的操作的信号和由中间电压产生电路产生的电压电平。

3. 发明授权

US4243975A Analog-to-digital converter 失效
公开(公告)号：US4243975A
公开(公告)日：1981-01-06
申请号：US945641
申请日：1978-09-25
申请人： Eiji Masuda , Yasoji Suzuki
发明人： Eiji Masuda , Yasoji Suzuki
IPC分类号： H03M1/52 , H03M1/00 , H03K13/20
CPC分类号： H03M1/183 , H03M1/52
摘要： A first reference voltage, a second reference voltage and an unknown analog signal with the same polarity with respect to that of the first reference voltage are applied in a given sequence to the second input of an integrator whose first input is supplied with a voltage which is half the difference between the first and second reference voltages. The output of the integrator is coupled with the second input of a comparator whose first input is supplied with a medium voltage between the second reference voltage and the input voltage at the first input of the integrator as a comparing reference voltage. At the beginning of conversion, the integrator initiates integration from the comparing reference voltage level. During first and second periods each having a given duration, the second reference voltage and the unknown analog signal are sequentially applied to the second input of the integrator. During a third period, the first reference voltage is applied to the second input of the integrator. A first counter counts clock pulses with a given frequency during the third period to thereby provide a digital value corresponding to the unknown analog signal. When the magnitude of the unknown analog signal is slightly smaller than the first reference voltage and when it is slightly larger than the second reference voltage, a digital value corresponding to the difference between the magnitudes of the unknown analog signal and the reference voltage is measured by a second counter. In another embodiment of the invention, one calibration cycle is executed for a series of conversion cycles of unknown analog signals. In the calibration cycle, a digital value, which includes an error due to an input offset voltage of the integrator, corresponding to the first of second reference voltage, is measured. The measured digital value of each unknown analog signal is calibrated depending on the difference between the measured digital value for a reference voltage including the error and a known correct digital value for the reference voltage.

4. 发明授权

US4267517A Operational amplifier 失效
标题翻译：运算放大器
公开(公告)号：US4267517A
公开(公告)日：1981-05-12
申请号：US965475
申请日：1978-12-01
申请人： Tetsuya Iida , Chikara Sato , Yasoji Suzuki
发明人： Tetsuya Iida , Chikara Sato , Yasoji Suzuki
IPC分类号： H03F1/30 , H03F3/30 , H03F3/45 , H03F3/16
CPC分类号： H03F1/308 , H03F3/3023 , H03F3/45183 , H03F3/45717 , H03F2203/45508 , H03F2203/45684
摘要： An operational amplifier is provided with a differential amplifier constructed by MOS transistors and a linear amplifier constructed by MOS transistors and coupled with the differential amplifier. The differential amplifier is supplied with first and second inputs. The output of the operational amplifier is derived from the output of the linear amplifier. A stabilizing circuit, which is coupled with the differential and linear amplifiers, stabilizes the output of the operational amplifier against a variation of the input DC levels to the differential amplifier.
摘要翻译：运算放大器配有由MOS晶体管构成的差分放大器和由MOS晶体管构成并与差分放大器耦合的线性放大器。差分放大器提供第一和第二输入。运算放大器的输出源自线性放大器的输出。与差分放大器和线性放大器耦合的稳定电路可以稳定运算放大器的输出，以抵抗差分放大器的输入直流电平的变化。

5. 发明授权

US06046626A Voltage transfer circuit and a booster circuit, and an IC card comprising the same 失效
标题翻译：电压传输电路和升压电路，以及包括该电路的IC卡
公开(公告)号：US06046626A
公开(公告)日：2000-04-04
申请号：US3946
申请日：1998-01-08
申请人： Yukihiro Saeki , Yasoji Suzuki
发明人： Yukihiro Saeki , Yasoji Suzuki
IPC分类号： G11C11/413 , G06K19/07 , G11C11/407 , G11C16/06 , H02M3/07 , H03K19/0948 , G05F3/02
CPC分类号： H02M3/073
摘要： A voltage transfer circuit comprises a first MOS transistor of a first channel type having a drain terminal connected to a first node supplied with a predetermined voltage, a source terminal connected to a second node, and a gate terminal, a second MOS transistor of a first channel type having a source terminal connected to the second node, a drain terminal connected to the gate terminal of the first MOS transistor, and a gate terminal supplied with a clock signal, as well as a third MOS transistor of a second channel type having a drain terminal connected to the drain terminal of the second MOS transistor, a source terminal connected to a third node supplied with a reference voltage, and a gate terminal supplied with the clock signal.
摘要翻译：电压传输电路包括第一通道类型的第一MOS晶体管，其具有连接到被提供有预定电压的第一节点的漏极端子，连接到第二节点的源极端子和栅极端子，第一MOS晶体管的第一沟道型，具有连接到第二节点的源极端子，连接到第一MOS晶体管的栅极端子的漏极端子和提供有时钟信号的栅极端子，以及具有第二沟道类型的第三MOS晶体管，其具有漏极端子连接到第二MOS晶体管的漏极端子，连接到提供有参考电压的第三节点的源极端子和被提供有时钟信号的栅极端子。

6. 发明授权

US6020869A Multi-gray level display apparatus and method of displaying an image at many gray levels 失效
公开(公告)号：US6020869A
公开(公告)日：2000-02-01
申请号：US841389
申请日：1997-04-30
申请人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
发明人： Itsuo Sasaki , Yasoji Suzuki , Hirofumi Kato , Isao Arita , Toshio Yanagisawa , Kazuyoshi Yamamoto , Hiroyoshi Murata , Hiroyuki Hamagawa
IPC分类号： G09G3/20 , G09G3/36 , G09G3/28 , G09G3/30 , G09G5/10
CPC分类号： G09G3/3648 , G09G2310/027 , G09G3/2007 , G09G3/2018
摘要： A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

7. 发明授权

US4558234A Complementary MOSFET logic circuit 失效
标题翻译：互补MOSFET逻辑电路
公开(公告)号：US4558234A
公开(公告)日：1985-12-10
申请号：US652429
申请日：1984-09-20
申请人： Yasoji Suzuki , Kenji Matsuo
发明人： Yasoji Suzuki , Kenji Matsuo
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092 , H03K19/003 , H03K19/01 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： Disclosed is a complementary MOSFET logic circuit having a complementary MOS inverter with a pregiven ratio of the channel widths of a P channel MOSFET and an N channel MOSFET and pregiven threshold voltages of the FETs so as to have an input voltage characteristic adapted to an output voltage characteristic, and a buffer circuit which includes a bipolar transistor for receiving at the base thereof a signal from the output terminal of the complementary MOS inverter and an N channel MOSFET for receiving at the gate thereof an input signal applied to the complementary MOS inverter. The inverter and buffer are connected in series to one another between a high potential applying point and a low potential applying point, and a signal corresponding to a logic output signal of the complementary MOS inverter is produced at the output terminal thereof.
摘要翻译：公开了具有互补MOS反相器的互补MOSFET逻辑电路，其具有P沟道MOSFET和N沟道MOSFET的沟道宽度的预制比和FET的预定阈值电压，以便具有适于输出电压的输入电压特性特性和缓冲电路，其包括用于在其基极处接收来自互补MOS反相器的输出端的信号的双极晶体管和用于在其栅极处接收施加到互补MOS反相器的输入信号的N沟道MOSFET。反相器和缓冲器在高电位施加点和低电位施加点之间彼此串联连接，并且在其输出端产生与互补MOS反相器的逻辑输出信号相对应的信号。

8. 发明授权

US4546327A Analog signal power amplifier circuit 失效
标题翻译：模拟信号功率放大器电路
公开(公告)号：US4546327A
公开(公告)日：1985-10-08
申请号：US513308
申请日：1983-07-13
申请人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
发明人： Yasoji Suzuki , Itsuo Sasaki , Shouji Abou
IPC分类号： H03F3/20 , H03F3/213 , H03F3/45 , H03F3/72
CPC分类号： H03F3/213 , H03F3/45183 , H03F3/72 , H03F2200/03 , H03F2200/507 , H03F2200/522 , H03F2203/45508 , H03F2203/45674
摘要： A signal corresponding to an analog input signal is supplied to one of two input terminals of a two-input, one-output MOS differential amplifier. A reference voltage signal is supplied to the other of the two input terminals of the MOS differential amplifier. A bipolar transistor having one end connected to an analog signal output terminal is driven by a signal from the output terminal of the MOS differential amplifier. A loudspeaker is driven by the bipolar transistor.
摘要翻译：对应于模拟输入信号的信号被提供给双输入一输出MOS差分放大器的两个输入端中的一个。将参考电压信号提供给MOS差分放大器的两个输入端子中的另一个。具有连接到模拟信号输出端的一端的双极晶体管由来自MOS差分放大器的输出端的信号驱动。扬声器由双极晶体管驱动。

9. 发明授权

US4280272A Method for preparing complementary semiconductor device 失效
标题翻译：互补半导体器件的制备方法
公开(公告)号：US4280272A
公开(公告)日：1981-07-28
申请号：US85595
申请日：1979-10-17
申请人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
发明人： Hideharu Egawa , Koji Matsuki , Yasoji Suzuki
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/22 , H01L21/265
CPC分类号： H01L21/823807 , H01L27/0928
摘要： A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.
摘要翻译：互补半导体器件包括分别形成在半导体衬底中并具有基本相同的杂质浓度的P型和N型半导体区域。 N沟道型和P沟道型硅栅极场效应晶体管分别形成在P沟道型和N沟道型区域中。 P型和N沟道型硅栅场效应晶体管的栅电极由相同导电类型的多晶硅形成。相同导电类型的杂质被掺杂到两个半导体区域中以提供沟道掺杂区域。

10. 发明授权

US4264968A Basic circuit for electronic timepieces 失效
标题翻译：电子钟表基本电路
公开(公告)号：US4264968A
公开(公告)日：1981-04-28
申请号：US864714
申请日：1977-12-27
申请人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
发明人： Yasoji Suzuki , Fuminari Tanaka , Yasushi Sato
IPC分类号： G01R19/00 , G04G3/02 , G04G9/00 , G04G99/00 , G04C3/00
CPC分类号： G04G99/00 , G04G3/022
摘要： There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.
摘要翻译：提供了一种电子钟表基本电路，包括用于产生1Hz脉冲的脉冲发生电路，具有包括连接到脉冲发生电路的输出端的端子的多个端子的第一端子组，具有端子的第二端子组分别连接到第一终端组的终端，与第二终端组耦合的10个比例计数器，连接到10个比例计数器的6个比例计数器，显示单元和与10个比例计数器耦合的解码器，6 缩放计数器并解码10和6比例计数器的内容，并将解码的内容传送到显示单元。第一和第二端子组彼此适当地联接。 10个刻度计数器和6个刻度计数器的组合被适当修改，以便根据需要形成12个，24个或60个刻度计数器。

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