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1. 发明授权

US07787301B2 Flash memory device using double patterning technology and method of manufacturing the same 有权
标题翻译：使用双重图案化技术的闪存器件及其制造方法
公开(公告)号：US07787301B2
公开(公告)日：2010-08-31
申请号：US11590207
申请日：2006-10-31
申请人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
发明人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
IPC分类号： G11C16/06
CPC分类号： H01L27/11531 , H01L27/11526
摘要： Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
摘要翻译：提供一种闪速存储器件及其制造方法。闪存设备包括字符串。串中的每一个具有字符串选择线，接地选择线和在串选择线和地选择线之间形成的奇数个字线。

2. 发明申请

US20100290285A1 Flash Memory Device Using Double Patterning Technology and Method of Manufacturing the Same 审中-公开
标题翻译：使用双重图案化技术的闪存设备及其制造方法
公开(公告)号：US20100290285A1
公开(公告)日：2010-11-18
申请号：US12845829
申请日：2010-07-29
申请人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
发明人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
IPC分类号： G11C16/04 , H01L21/768
CPC分类号： H01L27/11531 , H01L27/11526
摘要： Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
摘要翻译：提供一种闪速存储器件及其制造方法。闪存设备包括字符串。串中的每一个具有字符串选择线，接地选择线和在串选择线和地选择线之间形成的奇数个字线。

3. 发明申请

US20080067550A1 Flash memory device using double patterning technology and method of manufacturing the same 有权
标题翻译：使用双重图案化技术的闪存器件及其制造方法
公开(公告)号：US20080067550A1
公开(公告)日：2008-03-20
申请号：US11590207
申请日：2006-10-31
申请人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
发明人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Cha-won Koh , Pan-suk Kwak
IPC分类号： H01L27/10
CPC分类号： H01L27/11531 , H01L27/11526
摘要： Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.
摘要翻译：提供一种闪速存储器件及其制造方法。闪存设备包括字符串。串中的每一个具有字符串选择线，接地选择线和在串选择线和地选择线之间形成的奇数个字线。

4. 发明授权

US08026044B2 Method of forming fine patterns of semiconductor device 失效
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US08026044B2
公开(公告)日：2011-09-27
申请号：US11781987
申请日：2007-07-24
申请人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Pan-suk Kwak , Min-jong Hong
发明人： Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Pan-suk Kwak , Min-jong Hong
IPC分类号： G03F7/00 , G03F7/004 , G03F7/20 , G03F7/26 , G03F7/40
CPC分类号： H01L21/0337
摘要： A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.
摘要翻译：在半导体衬底上形成精细图案的方法包括形成包括具有特征尺寸F和任意间距P的第一线图案的第一图案，以及形成包括布置在相邻第一线图案之间的第二线图案的第二图案，以形成具有半间距P / 2的精细图案，第一和第二线图案沿第一方向重复。在与第一方向垂直的第二方向上的至少一个第一线图案中形成间隙，以通过间隙连接位于第一线图案的每一侧上的第二线图案。至少一个沿着第一方向延伸的点动图案由与连接的第二线图案相邻的至少一个第一线图案形成。所述点动图案在所述第二方向上在所连接的第二线图案中的至少一个中形成间隙。

5. 发明申请

US20080124931A1 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US20080124931A1
公开(公告)日：2008-05-29
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

6. 发明授权

US07892982B2 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US07892982B2
公开(公告)日：2011-02-22
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

7. 发明授权

US08339849B2 Semiconductor device and layout method for the semiconductor device 有权
标题翻译：半导体器件的半导体器件和布局方法
公开(公告)号：US08339849B2
公开(公告)日：2012-12-25
申请号：US12498833
申请日：2009-07-07
申请人： Pan-suk Kwak , Doo-youl Lee
发明人： Pan-suk Kwak , Doo-youl Lee
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： H01L27/0203 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573
摘要： Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).
摘要翻译：提供一种半导体器件，包括：多个位线图案; 分别连接到所述多个位线图案的多个焊盘图案; 以及形成在所述多个焊盘图案中的每一个上的至少一个触点，其中所述多个焊盘图案的间距大于所述多个位线图案的间距。位线图案可以使用双重图案化技术（DPT）形成。

8. 发明授权

US07804716B2 Flash memory device having improved bit-line layout and layout method for the flash memory device 有权
标题翻译：具有改进的位线布局和闪存设备的布局方法的闪存设备
公开(公告)号：US07804716B2
公开(公告)日：2010-09-28
申请号：US12222073
申请日：2008-08-01
申请人： Pan-suk Kwak , Doo-youl Lee
发明人： Pan-suk Kwak , Doo-youl Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L27/11519
摘要： Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage.
摘要翻译：提供了一种具有改进的位线布局和用于闪存设备的布局方法的闪存设备。基于双重图案形成技术（DPT）布置位线的闪速存储器件可以包括连接到包括存储数据的存储单元的单元串的至少一个主位线，至少一个平行于at 至少一个主位线和公共源极线传输公共源电压，并且设置在与其上设置有至少一个主位线和至少一个虚拟位线的层不同的层上，其中至少一个虚拟位线可以包括传送第一电压的第一虚拟位线和传送第二电压的第二虚拟位线。

9. 发明申请

US20100124114A1 Semiconductor Device and Layout Method for the Semiconductor Device 有权
标题翻译：半导体器件的半导体器件和布局方法
公开(公告)号：US20100124114A1
公开(公告)日：2010-05-20
申请号：US12498833
申请日：2009-07-07
申请人： Pan-suk Kwak , Doo-youl Lee
发明人： Pan-suk Kwak , Doo-youl Lee
IPC分类号： G11C16/04 , H01L21/82 , H01L29/00
CPC分类号： H01L27/0203 , H01L27/11519 , H01L27/11526 , H01L27/11565 , H01L27/11573
摘要： Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).
摘要翻译：提供一种半导体器件，包括：多个位线图案; 分别连接到所述多个位线图案的多个焊盘图案; 以及形成在所述多个焊盘图案中的每一个上的至少一个触点，其中所述多个焊盘图案的间距大于所述多个位线图案的间距。位线图案可以使用双重图案化技术（DPT）形成。

10. 发明申请

US20090034336A1 Flash memory device having improved bit-line layout and layout method for the flash memory device 有权
标题翻译：具有改进的位线布局和闪存设备的布局方法的闪存设备
公开(公告)号：US20090034336A1
公开(公告)日：2009-02-05
申请号：US12222073
申请日：2008-08-01
申请人： Pan-suk Kwak , Doo-youl Lee
发明人： Pan-suk Kwak , Doo-youl Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/11519
摘要： Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage.
摘要翻译：提供了一种具有改进的位线布局和用于闪存设备的布局方法的闪存设备。基于双重图案形成技术（DPT）布置位线的闪速存储器件可以包括连接到包括存储数据的存储单元的单元串的至少一个主位线，至少一个平行于at 至少一个主位线和公共源极线传输公共源电压，并且设置在与其上设置有至少一个主位线和至少一个虚拟位线的层不同的层上，其中至少一个虚拟位线可以包括传送第一电压的第一虚拟位线和传送第二电压的第二虚拟位线。

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