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1. 发明授权

US06970014B1 Routing architecture for a programmable logic device 失效
标题翻译：可编程逻辑器件的路由架构
公开(公告)号：US06970014B1
公开(公告)日：2005-11-29
申请号：US10623709
申请日：2003-07-21
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.
摘要翻译：本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反侧。功能块第三侧的输入和输出连接到第三个通道。与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

2. 发明授权

US06630842B1 Routing architecture for a programmable logic device 有权
公开(公告)号：US06630842B1
公开(公告)日：2003-10-07
申请号：US10140287
申请日：2002-05-06
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Brian D. Johnson , Richard Cliff , Srinivas T. Reddy , Christopher F. Lane , Cameron R. McClintock , Vaughn Betz , Chris Wysocki , Alexander R. Marquardt
IPC分类号： H03K19177
CPC分类号： H03K19/17736
摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

3. 发明授权

US06462577B1 Configurable memory structures in a programmable logic device 有权
标题翻译：可编程逻辑器件中的可配置存储器结构
公开(公告)号：US06462577B1
公开(公告)日：2002-10-08
申请号：US09761608
申请日：2001-01-16
申请人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
发明人： Andy L. Lee , Christopher F. Lane , Srinivas T. Reddy , Brian D. Johnson , Ketan H. Zaveri , Mario Guzman , Quyen Doan
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G11C8/12 , H03K19/17728
摘要： A programmable logic device is provided in which logic array blocks (LABs) may be programmably configured for use as one of a variety of memory structures. The configurable memory structures may have separate read and write addresses, thereby making it possible to implement a variety of memory structures such as FIFO memory, ROM, RAM, and shift-registers.
摘要翻译：提供了一种可编程逻辑器件，其中可编程地将逻辑阵列块（LAB）配置为用作各种存储器结构之一。可配置的存储器结构可以具有单独的读和写地址，从而使得可以实现各种存储器结构，例如FIFO存储器，ROM，RAM和移位寄存器。

4. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

5. 发明授权

US06356110B1 Multifunction memory array in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多功能存储器阵列
公开(公告)号：US06356110B1
公开(公告)日：2002-03-12
申请号：US09675727
申请日：2000-09-29
申请人： Srinivas T. Reddy , Brian D. Johnson , Christopher F. Lane , Ketan H. Zaveri
发明人： Srinivas T. Reddy , Brian D. Johnson , Christopher F. Lane , Ketan H. Zaveri
IPC分类号： H01L2501
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).
摘要翻译：提供了可编程选择性地配置用作多功能存储器阵列的逻辑阵列块（LAB）。 LAB可配置为至少两种模式运行：在第一种模式下，LAB内的每个逻辑单元均可单独配置以执行逻辑功能; 在第二模式中，逻辑元件可共同用作多功能存储器阵列。多功能存储器阵列可以在具有单独的读和写地址的基于LAB的基础上寻址，使得其可以被配置为实现各种存储器方案，包括先进先出（FIFO）存储器和随机存取存储器（随机存取存储器）。

6. 发明授权

US07287189B1 I/O configuration and reconfiguration trigger through testing interface 有权
标题翻译：通过测试界面进行I / O配置和重新配置触发
公开(公告)号：US07287189B1
公开(公告)日：2007-10-23
申请号：US10603888
申请日：2003-06-25
申请人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
发明人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
IPC分类号： G06F11/00
CPC分类号： G01R31/318572
摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.
摘要翻译：可重构设备在测试期间从诊断接口加载I / O配置信息。该设备包括用于与其他设备通信值的可配置I / O连接。诊断接口将I / O连接的值传送给测试仪。设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式接口，从而修改I / O连接的配置。该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。诊断接口可以是JTAG接口。

7. 发明授权

US06859065B2 Use of dangling partial lines for interfacing in a PLD 失效
标题翻译：使用悬挂的部分线路在PLD中进行接口
公开(公告)号：US06859065B2
公开(公告)日：2005-02-22
申请号：US10650465
申请日：2003-08-27
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
摘要翻译： PLD中的路由结构以交错方式实现。否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

8. 发明授权

US06653862B2 Use of dangling partial lines for interfacing in a PLD 有权
公开(公告)号：US06653862B2
公开(公告)日：2003-11-25
申请号：US10140911
申请日：2002-05-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

9. 发明申请

US20110260751A1 MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE 有权
标题翻译：多种数据速率记忆接口架构
公开(公告)号：US20110260751A1
公开(公告)日：2011-10-27
申请号：US13176284
申请日：2011-07-05
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

10. 发明授权

US08593195B1 High performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08593195B1
公开(公告)日：2013-11-26
申请号：US13614526
申请日：2012-09-13
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03H11/16
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

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