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1. 发明授权

US06268624B1 Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
标题翻译：在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法
公开(公告)号：US06268624B1
公开(公告)日：2001-07-31
申请号：US09364982
申请日：1999-07-31
申请人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
发明人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.
摘要翻译：制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

2. 发明授权

US06337246B1 Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
标题翻译：在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法
公开(公告)号：US06337246B1
公开(公告)日：2002-01-08
申请号：US09824841
申请日：2001-04-02
申请人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
发明人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.
摘要翻译：制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

3. 发明授权

US06531347B1 Method of making recessed source drains to reduce fringing capacitance 有权
标题翻译：制造凹陷式源极漏极以减少边缘电容的方法
公开(公告)号：US06531347B1
公开(公告)日：2003-03-11
申请号：US09776713
申请日：2001-02-06
申请人： Carl R. Huster , Judy An , Richard P. Rouse
发明人： Carl R. Huster , Judy An , Richard P. Rouse
IPC分类号： H01L2184
CPC分类号： H01L29/66636
摘要： The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming source and drain regions that are recessed a prescribed depth below the main surface of the semiconductor substrate. Sidewall spacers and a silicide layer are subsequently formed on the gate electrode stack. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.
摘要翻译：通过形成在半导体衬底的主表面下方以规定深度凹陷的源极和漏极区域来减小半导体器件的栅极电极和源极/漏极区域之间的电容。随后在栅极电极堆叠上形成侧壁间隔物和硅化物层。所得到的半导体器件在保持电路可靠性的同时，在栅极电极和源极/漏极区域之间表现出减小的电容。

4. 发明授权

US06487121B1 Method of programming a non-volatile memory cell using a vertical electric field 有权
标题翻译：使用垂直电场对非易失性存储单元进行编程的方法
公开(公告)号：US06487121B1
公开(公告)日：2002-11-26
申请号：US09899721
申请日：2001-07-05
申请人： Timothy J. Thurgate , Carl R. Huster
发明人： Timothy J. Thurgate , Carl R. Huster
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括在通道内施加横向电场，该横向电场产生在耗尽层的底部具有电子的耗尽层，并且在通道内施加具有足够强度的垂直电场，使得底部的电子耗尽层被注入到电荷捕获区域中。

5. 发明授权

US06667512B1 Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) 有权
标题翻译：不对称逆向卤素金属氧化物半导体场效应晶体管（MOSFET）
公开(公告)号：US06667512B1
公开(公告)日：2003-12-23
申请号：US09539577
申请日：2000-03-31
申请人： Carl R. Huster , Concetta Riccobene
发明人： Carl R. Huster , Concetta Riccobene
IPC分类号： H01L2976
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side. A retrograde HALO doped area is formed in the source side of the channel using tilted ion implantation. A source and drain are formed in the substrate adjacent to the source and drain sides of the channel. The asymmetrical doping arrangement provides the specified level of off-state leakage current without decreasing saturation drive current and transconductance.
摘要翻译：非对称逆行HALO金属氧化物半导体场效应晶体管（MOSFET）包括半导体衬底。栅极形成在衬底上，栅极在衬底中限定了一个沟道，其中源极侧和漏极侧均为基底。使用倾斜离子注入在沟道的源极侧形成逆行HALO掺杂区域。源极和漏极形成在与沟道的源极和漏极侧相邻的衬底中。非对称掺杂布置提供了指定电平的截止状态漏电流，而不降低饱和驱动电流和跨导。

6. 发明授权

US06395606B1 MOSFET with metal in gate for reduced gate resistance 有权
标题翻译：栅极中具有金属的MOSFET，用于降低栅极电阻
公开(公告)号：US06395606B1
公开(公告)日：2002-05-28
申请号：US09357918
申请日：1999-07-21
申请人： Carl R. Huster , Ognjen Milic-Strkalj , Emi Ishida
发明人： Carl R. Huster , Ognjen Milic-Strkalj , Emi Ishida
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28123 , H01L29/42376 , H01L29/66537 , H01L29/66553
摘要： A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided. The sidewall spacers and the nitride layer block the channel implant from the source/drain areas, thereby reducing parasitic junction capacitance, and the metal layer extending from above the gate oxide layer to the top of the gate reduces gate resistance, thereby increasing the switching speed of the finished device.
摘要翻译：形成具有降低的寄生结电容和减小的栅极电阻的MOS半导体器件。实施例包括在露出衬底的氮化物层中的开口的侧表面上形成氧化物侧壁间隔物，以及执行沟道植入。然后在衬底的暴露部分上热生长薄的栅极氧化物层，并且在栅极氧化物层和间隔物上沉积相对薄的多晶硅层。然后沉积诸如钨的金属层，填充开口，并且通过化学机械抛光使用氮化物层作为抛光停止来平坦化。之后通过离子注入形成源极/漏极区，并且源/漏区被硅化。侧壁间隔物和氮化物层阻挡从源极/漏极区域的沟道注入，由此减小寄生结电容，并且从栅极氧化物层上方延伸到栅极顶部的金属层降低栅极电阻，从而增加开关速度的成品设备。

7. 发明授权

US06225229B1 Removable photoresist spacers in CMOS transistor fabrication 有权
标题翻译： CMOS晶体管制造中的可移动光刻胶隔离物
公开(公告)号：US06225229B1
公开(公告)日：2001-05-01
申请号：US09317157
申请日：1999-05-24
申请人： Carl R. Huster
发明人： Carl R. Huster
IPC分类号： H01L21312
CPC分类号： H01L21/823864 , H01L21/312 , H01L29/6659 , Y10S438/947
摘要： Removable photoresist sidewall spacers are formed on side surfaces of device features, such as gate electrodes, enabling simplifying CMOS methodology by reducing the number of critical masks and processing steps. Embodiments included angular exposure of a photoresist layer using the device feature to shadow the photoresist on the side surface, thereby preventing exposure such that the unexposed photoresist portion is not removed during subsequent development. Embodiments of the present invention also include forming removable, photoresist sidewall spacers on the side surfaces of the gates of NMOS and PMOS transistors, forming moderately or heavily doped source/drain implants, activation annealing to form moderately or heavily doped source/drain regions, ion implanting shallow source/drain extensions and halo regions and activating the shallow extensions and halo regions.
摘要翻译：可移动光致抗蚀剂侧壁间隔物形成在诸如栅电极的器件特征的侧表面上，通过减少关键掩模和处理步骤的数量，可以简化CMOS方法。实施例包括使用该器件特征对光致抗蚀剂层进行角度曝光以遮蔽侧表面上的光致抗蚀剂，由此防止曝光，使得未曝光的光致抗蚀剂部分在随后的显影期间不被去除。本发明的实施例还包括在NMOS和PMOS晶体管的栅极的侧表面上形成可移除的光致抗蚀剂侧壁间隔物，形成适度或重掺杂的源极/漏极注入，激活退火以形成适度或重掺杂的源极/漏极区域，离子注入浅源极/漏极延伸部分和晕圈区域并激活浅延伸部分和晕圈。

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