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    • 1. 发明申请
    • PROGRAMMABLE READ PREAMBLE
    • 可编程阅读前置
    • US20110179215A1
    • 2011-07-21
    • US12691633
    • 2010-01-21
    • Clifford Alan ZitlawAnthony Le
    • Clifford Alan ZitlawAnthony Le
    • G06F12/00G06F12/02
    • G11C16/20G11C7/1072G11C7/20
    • The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
    • 主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。 高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式,其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式,其中在高速存储器上电之后加载默认前导码模式。 可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。 另外,可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。
    • 2. 发明授权
    • Variable read latency on a serial memory bus
    • 串行存储器总线上的可变读延迟
    • US08291126B2
    • 2012-10-16
    • US12729905
    • 2010-03-23
    • Clifford Alan Zitlaw
    • Clifford Alan Zitlaw
    • G06F3/00G06F13/00
    • G06F13/161G06F13/4291
    • One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.
    • 一个或多个实施例提供了通过串行输入/输出存储器数据接口从可变延迟存储器读取数据的方法和系统。 该系统包括具有可变延迟访问时间的存储器,存储器控制器和将存储器控制器耦合到存储器的串行数据总线。 存储器控制器将Read命令传送到存储器,并在有限的时间内迫使串行数据总线为低电平。 然后存储器强制总线为低电平,然后存储器控制器释放总线。 当存储器准备好提供数据时,存储器在串行数据总线上提供高信号。
    • 4. 发明申请
    • APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE
    • 使用预读数据捕获数据的装置和方法
    • US20120063243A1
    • 2012-03-15
    • US12880018
    • 2010-09-10
    • Qamrul HasanClifford Alan ZitlawStephan RosnerDubois Sylvain
    • Qamrul HasanClifford Alan ZitlawStephan RosnerDubois Sylvain
    • G11C7/06G11C8/18
    • G11C7/1093G11C29/022G11C29/028
    • A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.
    • 提供数据采集装置。 数据采集​​装置包括数据采集装置控制器和数据采集部件。 数据捕获装置被配置为发送突发读取命令。 每个数据捕获组件包括DLL组件,数据采样组件,比较组件和有效时钟计算组件。 DLL组件被设置成提供时钟信号。 数据采样部件被布置为接收包括读取前置码的串行数据信号,其中读取前同步码包括训练模式,并且利用每个时钟信号对串行数据信号进行采样。 比较部件被布置为将每个采样数据信号与预期的训练模式进行比较。 有效时钟计算部件被配置为基于比较,选择一个时钟信号作为用于锁定DLL组件的有效时钟信号。
    • 9. 发明授权
    • Apparatus and method for data capture using a read preamble
    • 使用读取前同步码进行数据采集的装置和方法
    • US08140778B1
    • 2012-03-20
    • US12880018
    • 2010-09-10
    • Qamrul HasanClifford Alan ZitlawStephan RosnerDubois Sylvain
    • Qamrul HasanClifford Alan ZitlawStephan RosnerDubois Sylvain
    • G06F13/00G06F13/28H04L7/00
    • G11C7/1093G11C29/022G11C29/028
    • A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.
    • 提供数据采集装置。 数据采集​​装置包括数据采集装置控制器和数据采集部件。 数据捕获装置被配置为发送突发读取命令。 每个数据捕获组件包括DLL组件,数据采样组件,比较组件和有效时钟计算组件。 DLL组件被设置成提供时钟信号。 数据采样部件被布置为接收包括读取前置码的串行数据信号,其中读取前同步码包括训练模式,并且利用每个时钟信号对串行数据信号进行采样。 比较部件被布置为将每个采样数据信号与预期的训练模式进行比较。 有效时钟计算部件被配置为基于比较,选择一个时钟信号作为用于锁定DLL组件的有效时钟信号。