专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06828620B2 Nonvolatile memory cell with low doping region 失效
标题翻译：具有低掺杂区域的非易失性存储单元
公开(公告)号：US06828620B2
公开(公告)日：2004-12-07
申请号：US10436644
申请日：2003-05-12
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L29788
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
摘要翻译：制造非易失性器件的技术包括形成低掺杂区域以有助于还原衬底热电子。非易失性器件可以是诸如闪存，EEPROM或EPROM存储器单元的浮动栅极器件。低掺杂区域的掺杂浓度低于衬底的掺杂浓度。通过减少衬底热电子，这提高了非易失性器件的可靠性和寿命。

2. 发明授权

US5949710A Programmable interconnect junction 失效
标题翻译：可编程互连结
公开(公告)号：US5949710A
公开(公告)日：1999-09-07
申请号：US741082
申请日：1996-10-30
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H03K19/177 , G11C11/34
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
摘要翻译：用于在集成电路中实现可编程互连的静态，非易失性和可编程可编程互连结单元。可编程互连结（600）可编程地配置为耦合或去耦第一互连线（210）和第二互连线（220）。直接检测可编程互连结的配置状态，并且在正常操作期间不需要诸如读出放大器的存储单元检测电路。全轨电压可以从第一互连线和第二互连线传递。

3. 发明授权

US6122209A Method of margin testing programmable interconnect cell 失效
标题翻译：可靠性测试方法可编程互连单元
公开(公告)号：US6122209A
公开(公告)日：2000-09-19
申请号：US350084
申请日：1999-07-08
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
摘要翻译：用于在集成电路中实现可编程互连的静态，非易失性和可编程可编程互连结单元。可编程互连结（600）可编程地配置为耦合或去耦第一互连线（210）和第二互连线（220）。直接检测可编程互连结的配置状态，并且在正常操作期间不需要诸如读出放大器的存储单元检测电路。全轨电压可以从第一互连线和第二互连线传递。

4. 发明授权

US06573138B1 Nonvolatile memory cell with low doping region 有权
公开(公告)号：US06573138B1
公开(公告)日：2003-06-03
申请号：US09349533
申请日：1999-07-08
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L21336
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

5. 发明授权

US5905675A Biasing scheme for reducing stress and improving reliability in EEPROM cells 失效
标题翻译：用于减小应力并提高EEPROM单元可靠性的偏置方案
公开(公告)号：US5905675A
公开(公告)日：1999-05-18
申请号：US995870
申请日：1997-12-22
申请人： Raminda U. Madurawe , Richard G. Smolen , Minchang Liang , James D. Sansbury , John E. Turner , John C. Costello , Myron W. Wong
发明人： Raminda U. Madurawe , Richard G. Smolen , Minchang Liang , James D. Sansbury , John E. Turner , John C. Costello , Myron W. Wong
IPC分类号： G11C16/04 , G11C16/26 , G11C29/50 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/3427 , G11C29/50 , G11C29/50004 , H01L27/115 , H01L27/11558 , G11C16/04 , G11C16/26 , G11C2216/10
摘要： Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.
摘要翻译：公开了一种用于偏置双行线EEPROM单元的方法。新的偏置方案通过减小控制栅极和单元的写入列之间的电位差来改善EEPROM单元的数据保持寿命，这降低了隧道氧化物电场。在优选实施例中，该方法包括将偏置电压施加到EEPROM单元的控制栅极和写入列，使得控制栅极与右列之间的电位差不超过约0.5伏特。通过将单元的写入列偏置为正电压，隧道氧化物场可能会显着减少。此外，本发明提供了一种基于控制栅极电压来选择写入列电压的方法，使得隧道氧化物场在其所有模式中基本平衡。该偏置方案使SILC最小化，并提高了单元的可靠性。

6. 发明授权

US06646919B1 Apparatus and method for margin testing single polysilicon EEPROM cells 失效
标题翻译：单个多晶硅EEPROM单元的边缘测试的装置和方法
公开(公告)号：US06646919B1
公开(公告)日：2003-11-11
申请号：US09874716
申请日：2001-06-04
申请人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
发明人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce F. Mielke
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译：公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除电池的裕度电压进入可测量范围。

7. 发明授权

US06781883B1 Apparatus and method for margin testing single polysilicon EEPROM cells 失效
标题翻译：单个多晶硅EEPROM单元的边缘测试的装置和方法
公开(公告)号：US06781883B1
公开(公告)日：2004-08-24
申请号：US10620917
申请日：2003-07-15
申请人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce E. Mielk
发明人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce E. Mielk
IPC分类号： G11C1606
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译：公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除电池的裕度电压进入可测量范围。

8. 发明授权

US06532170B1 Nonvolatile configuration cells and cell arrays 失效
标题翻译：非易失配置单元和单元阵列
公开(公告)号：US06532170B1
公开(公告)日：2003-03-11
申请号：US09921548
申请日：2001-08-02
申请人： Raminda U. Madurawe , James D. Sansbury
发明人： Raminda U. Madurawe , James D. Sansbury
IPC分类号： G11C1604
CPC分类号： G11C5/025 , G11C5/00 , G11C16/0416 , G11C16/0441 , H03K19/17748 , H03K19/1776 , H03K19/17772 , H03K19/1778 , H03K19/17784
摘要： A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (810). In one embodiment, the programmable memory element (810) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).
摘要翻译：用于将数据存储在集成电路中的存储单元（400）。存储单元（400）是静态的，非易失性的和可编程的。存储单元的布局紧凑。存储单元（400）的逻辑高电平输出约为VDD，逻辑低电平输出约为VSS。本发明的存储单元（400）包括可编程存储元件（810）。在一个实施例中，可编程存储元件（810）耦合在电源电压（510）和输出节点（405）之间。下拉装置（525）耦合在另一个电源电压（505）和输出节点（405）之间。存储单元（400）可用于存储可编程逻辑器件（121）的配置信息。

9. 发明授权

US06268623B1 Apparatus and method for margin testing single polysilicon EEPROM cells 失效
标题翻译：单个多晶硅EEPROM单元的边缘测试的装置和方法
公开(公告)号：US06268623B1
公开(公告)日：2001-07-31
申请号：US08995873
申请日：1997-12-22
申请人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce E. Mielke
发明人： Raminda U. Madurawe , Myron W. Wong , John C. Costello , James D. Sansbury , Bruce E. Mielke
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0441 , G11C16/26 , G11C16/3427 , G11C29/50 , G11C29/50004 , G11C2216/10 , H01L27/115 , H01L27/11558
摘要： Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
摘要翻译：公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。简而言之，本发明涉及将电池的阈值电压更高，导致余量电压的相应上升，从而可以在正电压范围内进行擦除裕度的测试。本发明实现了针对该问题的各种解决方案，包括在小区处理和电路中的创新。在一个实施例中，用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。或者，或者与这些一般的工艺变化相结合，浮栅晶体管的宽度可能会减小，导致余量电压的相应增加。电路修改包括提供单独的测试模式条件，其中感测放大器跳闸电流高于正常操作，并且通过新的感测放大器优化提高源极线路的电压电平，或者仅在裕度测试模式期间，两者都移动擦除电池的裕度电压进入可测量范围。

10. 发明授权

US6052309A Nonvolatile configuration cells and cell arrays 失效
公开(公告)号：US6052309A
公开(公告)日：2000-04-18
申请号：US386042
申请日：1999-08-30
申请人： Raminda U. Madurawe , James D. Sansbury
发明人： Raminda U. Madurawe , James D. Sansbury
IPC分类号： G11C5/00 , G11C16/04 , H03K19/177
CPC分类号： G11C5/025 , G11C16/0416 , G11C16/0441 , G11C5/00 , H03K19/17748 , H03K19/1776 , H03K19/17772 , H03K19/1778 , H03K19/17784
摘要： A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式