专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080014895A1 DIRECT CONVERSION RECEIVER ARCHITECTURE 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20080014895A1
公开(公告)日：2008-01-17
申请号：US11862330
申请日：2007-09-27
申请人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
发明人： Tao Li , Christian Holenstein , Inyup Kang , Brett Walker , Paul Peterzell , Raghu Challa , Matthew Severson , Arun Raghupathy , Gilbert Sih
IPC分类号： H04B1/26
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

2. 发明申请

US20050208916A1 Direct conversion receiver architecture 有权
标题翻译：直接转换接收机架构
公开(公告)号：US20050208916A1
公开(公告)日：2005-09-22
申请号：US11131147
申请日：2005-05-16
申请人： Paul Peterzell , Tao Li , Christian Holenstein , Inyup Kang , Matthew Severson
发明人： Paul Peterzell , Tao Li , Christian Holenstein , Inyup Kang , Matthew Severson
IPC分类号： H03G1/00 , H03G3/20 , H03G3/30 , H04L27/22 , H04L27/38 , H04B1/06 , H04B1/26 , H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供一系列增益的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

3. 发明授权

US06985711B2 Direct current offset cancellation for mobile station modems using direct conversion 失效
公开(公告)号：US06985711B2
公开(公告)日：2006-01-10
申请号：US10139205
申请日：2002-05-02
申请人： Christian Holenstein , Inyup Kang , Matthew Severson
发明人： Christian Holenstein , Inyup Kang , Matthew Severson
IPC分类号： H04B1/10
CPC分类号： H04L25/061 , H04B1/30
摘要： A system and method for canceling DC offset for Mobile Station Modems having direct conversion architectures. The present invention is a fast acquiring DC offset cancellation block that provides rapid and accurate DC offset estimates and cancellation techniques to support direct conversion architectures. The fast acquiring DC offset cancellation block combines four mechanisms to rapidly acquire and remove a DC offset estimate after power up, temperature changes, receiver frequency changes, and gain setting changes by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. After removing the DC offset in large portions, the high pass loop bandwidth is decreased to fine tune the previous estimate and to remove any small variation in DC offset due to receiver self-mixing products.

4. 发明申请

US20050218871A1 Dynamic voltage scaling for portable devices 有权
标题翻译：便携式设备的动态电压缩放
公开(公告)号：US20050218871A1
公开(公告)日：2005-10-06
申请号：US10814935
申请日：2004-03-30
申请人： Inyup Kang , Karthikeyan Ethirajan , Matthew Severson
发明人： Inyup Kang , Karthikeyan Ethirajan , Matthew Severson
IPC分类号： G05F1/40 , G06F1/32
CPC分类号： G05F1/40 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for voltage regulation uses, in one aspect, worst-case supply voltages specific to the process split of the integrated device at issue. In another aspect, a two-phase voltage regulation system and method identifies the characterization data pertinent to a family of integrated circuit devices in a first phase, and identifies an associated process split of a candidate integrated circuit device in a second phase. The characterization data from the first phase is then used to provide supply voltages that correspond to target frequencies of operation for the candidate device. In another aspect, a hybrid voltage regulator circuit includes an open loop circuit which automatically identifies the process split of the integrated circuit device and allows a regulator to modify supply voltage based on characterization data specific to that process split, and a closed loop circuit which fine-tunes the supply voltage. In one embodiment, the closed-loop circuit includes a critical path replica for providing estimated frequencies of operation necessary for a critical path in the integrated circuit device. A ring oscillator circuit may be used in one embodiment in the critical path and/or in the open loop circuit.
摘要翻译：一方面，用于电压调节的方法和装置在一个方面使用特定于所讨论的集成器件的工艺分裂的最坏情况的电源电压。在另一方面，两相电压调节系统和方法识别与第一阶段中的集成电路器件系列相关的特征数据，并且识别在第二阶段中候选集成电路器件的相关联的工艺分组。然后使用来自第一阶段的表征数据来提供对应于候选设备的目标操作频率的电源电压。另一方面，混合电压调节器电路包括开环电路，其自动识别集成电路器件的工艺分离，并且允许调节器基于该工艺分离特有的特性数据修改供电电压，以及闭环电路调节电源电压。在一个实施例中，闭环电路包括关键路径副本，用于提供集成电路设备中的关键路径所需的估计工作频率。在一个实施例中，在关键路径和/或开环电路中可以使用环形振荡器电路。

5. 发明申请

US20070214389A1 JTAG power collapse debug 审中-公开
标题翻译： JTAG电源崩溃调试
公开(公告)号：US20070214389A1
公开(公告)日：2007-09-13
申请号：US11370696
申请日：2006-03-07
申请人： Matthew Severson , Kevin Burke , Philip Pottier
发明人： Matthew Severson , Kevin Burke , Philip Pottier
IPC分类号： G06F11/00
CPC分类号： G06F11/3656
摘要： A method of performing a debug operation on a processor after a power collapse is provided. An idle state of the processor is detected during an execution mode of the processor. The idle state is determined to be associated with a power collapse event. A debug state of the processor is restored by loading debug registers within the processor during the execution mode.
摘要翻译：提供了在电源崩溃之后在处理器上执行调试操作的方法。在处理器的执行模式期间检测处理器的空闲状态。空闲状态被确定为与功率崩溃事件相关联。在执行模式期间，通过在处理器中加载调试寄存器来恢复处理器的调试状态。

6. 发明申请

US20060184808A1 Distributed supply current switch circuits for enabling individual power domains 有权
标题翻译：用于启用各个电源域的分布式电源电流开关电路
公开(公告)号：US20060184808A1
公开(公告)日：2006-08-17
申请号：US11228912
申请日：2005-09-16
申请人： Lew Chua-Eoan , Matthew Severson , Sorin Dobre , Tsvetornir Petrov , Rajat Goel
发明人： Lew Chua-Eoan , Matthew Severson , Sorin Dobre , Tsvetornir Petrov , Rajat Goel
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided.
摘要翻译：集成电路包括多个电源域。电源电流开关电路（SCSC）分布在每个电源域上。当SCSC中的控制节点上存在信号时，SCSC将电源域的本地电源总线耦合到全局电源总线。使能信号路径延伸穿过SCSC，使得使能信号可以从SCSC链从传播控制节点传播到控制节点，从而逐个转换SCSC。当域要加电时，控制电路断言使第一链SCSC向下传播的使能信号。在可编程的时间量之后，控制电路断言向下传播第二链的第二使能信号。通过随着时间推移SCSC的接通，避免了将局部和全局总线连接在一起的大电流。

7. 发明申请

US20050276132A1 Headswitch and footswitch circuitry for power management 有权
标题翻译：用于电源管理的头开关和脚踏开关电路
公开(公告)号：US20050276132A1
公开(公告)日：2005-12-15
申请号：US10856526
申请日：2004-05-27
申请人： Matthew Severson , Chih-tung Chen , Geoffrey Shippee , Sorin Dobre
发明人： Matthew Severson , Chih-tung Chen , Geoffrey Shippee , Sorin Dobre
IPC分类号： H03K19/00 , G11C7/00
CPC分类号： H03K19/0016
摘要： In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.
摘要翻译：通常，本公开涉及用于在用于电力管理的ASIC中实现头戴式开关和脚踏开关的电路。所公开的电路不仅支持有效的电源管理，而且还有效地利用ASIC区域，降低复杂性以及使用电子设计自动化（EDA）工具。以这种方式，所公开的电路可以支持增强的性能和简化的ASIC设计。在一些情况下，头开关或脚踏开关电路可以实现为围绕形成ASIC核心的一部分的宏宏延伸的开关板环。在其他情况下，通过将耦合到标准单元行的金属层功率路由嵌入分布式头部开关或脚踏开关组件，可将头开关或脚踏开关电路分布在ASIC内部。

8. 发明申请

US20050208919A1 Serial bus interface for direct conversion receiver 有权
标题翻译：用于直接转换接收器的串行总线接口
公开(公告)号：US20050208919A1
公开(公告)日：2005-09-22
申请号：US11131093
申请日：2005-05-16
申请人： Brett Walker , Paul Peterzell , Tao Li , Matthew Severson
发明人： Brett Walker , Paul Peterzell , Tao Li , Matthew Severson
IPC分类号： H03G1/00 , H03G3/20 , H03G3/30 , H04L27/22 , H04L27/38 , H04B1/06 , H04B1/10 , H04B7/00
CPC分类号： H03G3/3078 , H03G3/3068 , H03G3/3089
摘要： A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
摘要翻译：具有用于去除信号分量的DC偏移的DC环路的直接下变频接收机架构，提供增益范围的数字可变增益放大器（DVGA），用于为DVGA和RF提供增益控制的自动增益控制（AGC）回路 /模拟电路和串行总线接口（SBI）单元，通过串行总线为RF /模拟电路提供控制。可以如本文所述有利地设计和定位DVGA。可以基于DC循环的操作模式来选择VGA循环的操作模式，因为这两个循环彼此相互作用。在采集模式下，DC环路工作的持续时间可以被选择为与采集模式中的DC环路带宽成反比。一些或全部RF /模拟电路的控制可以通过串行总线提供。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式