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1. 发明授权

US07707530B2 Incremental timing-driven, physical-synthesis using discrete optimization 有权
标题翻译：使用离散优化的增量式时序驱动，物理合成
公开(公告)号：US07707530B2
公开(公告)日：2010-04-27
申请号：US11941105
申请日：2007-11-16
申请人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
发明人： Charles J. Alpert , Zhuo Li , Michael D. Moffitt , David A. Papa
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.
摘要翻译：一种用于优化物理合成流中子电路的逻辑门的布置的方法，数据处理系统和计算机程序产品。路径平滑实用程序基于至少一个选择标准识别一个或多个可移动门。生成与一个或多个识别的可移动门对应的一组合法化候选位置。然后生成基于生成的合法化候选位置集合的分离时序图。一个或多个可移动门的最佳位置使用递归分支搜索并被存储在计算设备中来确定。

2. 发明授权

US08108818B2 Method and system for point-to-point fast delay estimation for VLSI circuits 有权
标题翻译：用于VLSI电路的点对点快速延迟估计的方法和系统
公开(公告)号：US08108818B2
公开(公告)日：2012-01-31
申请号：US12363340
申请日：2009-01-30
申请人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
发明人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.
摘要翻译：本公开涉及一种用于估计在超大规模集成（VLSI）电路内的网络的源到汇路径的互连延迟的方法，所述源到宿路径连接源和汇中的源净。该方法可以包括估计总线电容; 基于多个非路径汇的源到汇路径和延迟的延迟来计算延迟贡献; 以及基于延迟贡献来估计源到汇路径的互连延迟。

3. 发明申请

US20100199243A1 METHOD AND SYSTEM FOR POINT-TO-POINT FAST DELAY ESTIMATION FOR VLSI CIRCUITS 有权
标题翻译：用于VLSI电路的点到点快速延迟估计的方法和系统
公开(公告)号：US20100199243A1
公开(公告)日：2010-08-05
申请号：US12363340
申请日：2009-01-30
申请人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
发明人： Chin Ngai Sze , Charles J. Alpert , Michael D. Moffitt , Zhuo Li
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.
摘要翻译：本公开涉及一种用于估计在超大规模集成（VLSI）电路内的网络的源到汇路径的互连延迟的方法，所述源到宿路径连接源和汇中的源净。该方法可以包括估计总线电容; 基于多个非路径汇的源到汇路径和延迟的延迟来计算延迟贡献; 以及基于延迟贡献来估计源到汇路径的互连延迟。

4. 发明申请

US20120317527A1 PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION 失效
标题翻译：硬件加速功能验证分区
公开(公告)号：US20120317527A1
公开(公告)日：2012-12-13
申请号：US13590115
申请日：2012-08-20
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

5. 发明授权

US08495535B2 Partitioning and scheduling uniform operator logic trees for hardware accelerators 失效
标题翻译：为硬件加速器分区和调度统一运算符逻辑树
公开(公告)号：US08495535B2
公开(公告)日：2013-07-23
申请号：US13305156
申请日：2011-11-28
申请人： Zoltan T. Hidvegi , Michael D. Moffitt , Matyas A. Sustik
发明人： Zoltan T. Hidvegi , Michael D. Moffitt , Matyas A. Sustik
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/04
摘要： A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.
摘要翻译：通过在保留节点信息的同时移除统一运算符树（例如，断言树）的内部门来编译用于硬件加速功能验证的电路设计，并且划分电路以优化连接性而不受统一运算符树的约束。分区后，为分区构建子树，并聚合形成主树。子树可以基于叶节点的等级具有不同深度的叶节点，并且主树可以基于子树的模拟深度类似地提供来自不同深度的子树的输入。重新合成的主树在结构上与原始统一运算符树不同，但是由于输入是可交换的（例如，或门），所以保留了模型的功能等同性。

6. 发明授权

US08141017B2 Method for bounded transactional timing analysis 有权
标题翻译：有界交易时间分析方法
公开(公告)号：US08141017B2
公开(公告)日：2012-03-20
申请号：US12237482
申请日：2008-09-25
申请人： David Papa , Michael D. Moffitt
发明人： David Papa , Michael D. Moffitt
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more changes are then made to the timing window and stored in the transaction history. The changed elements are marked as dirty and stored in the transaction history. After the one or more changes have been made, the timing window is queried for current timing conditions and compared with the checkpoint. If the one or more changes are an improvement, the one or more changes are committed by replicating the one or more changes to the portion of the gate-level netlist. If the one or more changes are not an improvement, the timing window may be restored to the checkpoint.
摘要翻译：选择表示集成电路设计的门级网表的一部分用于优化。制作代表选定部分的定时窗口，包括所选部分的一个或多个拷贝。为定时窗口创建检查点，并存储在事务历史记录中。然后对定时窗口进行一个或多个更改，并将其存储在交易历史中。更改的元素被标记为脏，并存储在事务历史记录中。在进行一次或多次更改之后，查询当前定时条件的定时窗口并与检查点进行比较。如果一个或多个改变是改进，则通过复制对门级网表的一部分的一个或多个改变来提交一个或多个改变。如果一个或多个更改不是改进，则定时窗口可以恢复到检查点。

7. 发明授权

US5231663A Image processing system 失效
标题翻译：图像处理系统
公开(公告)号：US5231663A
公开(公告)日：1993-07-27
申请号：US670715
申请日：1991-03-18
申请人： Joseph G. Earl , Michael D. Moffitt
发明人： Joseph G. Earl , Michael D. Moffitt
IPC分类号： G06K9/20
CPC分类号： G06K9/2054 , G06Q20/085
摘要： An image processing system receives a series of pixel elements representative of a scanned image. The system converts the pixel elements into a vector representation of the scanned image. The vector representation of the scanned image is compared with known vector representations. Based upon this comparison, the image processing system performs various functions such as providing an output or controlling the system. The image processing system may be used for mark sense recognition in which mark information is decoded from learned forms based upon a key. An output is provided based upon a comparison between the marks and the key.
摘要翻译：图像处理系统接收表示扫描图像的一系列像素元件。系统将像素元素转换成扫描图像的向量表示。将扫描图像的向量表示与已知矢量表示进行比较。基于该比较，图像处理系统执行各种功能，例如提供输出或控制系统。图像处理系统可以用于标记感知识别，其中基于密钥从学习形式对标记信息进行解码。基于标记和键之间的比较来提供输出。

8. 发明授权

US08555221B2 Partitioning for hardware-accelerated functional verification 失效
标题翻译：分区硬件加速功能验证
公开(公告)号：US08555221B2
公开(公告)日：2013-10-08
申请号：US13590115
申请日：2012-08-20
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

9. 发明授权

US08327304B2 Partitioning for hardware-accelerated functional verification 有权
标题翻译：分区硬件加速功能验证
公开(公告)号：US08327304B2
公开(公告)日：2012-12-04
申请号：US12949328
申请日：2010-11-18
申请人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
发明人： Michael D. Moffitt , Matyas A. Sustik , Paul G. Villarrubia
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译：使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。松弛可以计算为边缘来源的早期和晚期等级之间的差异。重量可以进一步计算为边缘的松弛和最大松弛值之间的差。在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。边缘和顶点权重可以重新计算下一级分区。分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。

10. 发明申请

US20100077368A1 Method for Bounded Transactional Timing Analysis 有权
标题翻译：有界事务定时分析方法
公开(公告)号：US20100077368A1
公开(公告)日：2010-03-25
申请号：US12237482
申请日：2008-09-25
申请人： David Papa , Michael D. Moffitt
发明人： David Papa , Michael D. Moffitt
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more changes are then made to the timing window and stored in the transaction history. The changed elements are marked as dirty and stored in the transaction history. After the one or more changes have been made, the timing window is queried for current timing conditions and compared with the checkpoint. If the one or more changes are an improvement, the one or more changes are committed by replicating the one or more changes to the portion of the gate-level netlist. If the one or more changes are not an improvement, the timing window may be restored to the checkpoint.
摘要翻译：选择表示集成电路设计的门级网表的一部分用于优化。制作代表选定部分的定时窗口，包括所选部分的一个或多个拷贝。为定时窗口创建检查点，并存储在事务历史记录中。然后对定时窗口进行一个或多个更改，并将其存储在交易历史中。更改的元素被标记为脏，并存储在事务历史记录中。在进行一次或多次更改之后，查询当前定时条件的定时窗口并与检查点进行比较。如果一个或多个改变是改进，则通过复制对门级网表的一部分的一个或多个改变来提交一个或多个改变。如果一个或多个更改不是改进，则定时窗口可以恢复到检查点。

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