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1. 发明授权

US5444719A Adjustable error-correction composite Reed-Solomon encoder/syndrome generator 失效
标题翻译：可纠正的纠错复合Reed-Solomon编码器/综合发生器
公开(公告)号：US5444719A
公开(公告)日：1995-08-22
申请号：US8922
申请日：1993-01-26
申请人： Charles E. Cox , Gerhard P. Fettweis , Martin A. Hassner , Uwe Schwiegelshohn
发明人： Charles E. Cox , Gerhard P. Fettweis , Martin A. Hassner , Uwe Schwiegelshohn
IPC分类号： G06F11/10 , G11B20/18 , H03M13/00 , H03M13/15 , H03M13/35
CPC分类号： G11B20/1833 , H03M13/151 , H03M13/35
摘要： A composite encoder/syndrome generating circuit computes both check symbols and error syndromes using a single set of multiplier devices with varying tap weights having values that provide a maximum preselected error correction capability but is readily adjustable, such as by programmable latches, to eliminate from the circuit selectable multiplier devices to reduce the error correction capability without requiring a change in the tap weight values. The circuit may be used to increase or decrease error correction capability (a) according to which of a plurality of concentric bands of recording tracks is being accessed in a banded direct access data storage device, (b) according to noise level as sensed in a data communications channel having an output subject to noise, or (c) according to changes in sending rates in a sending device that sends data at variable rates.
摘要翻译：复合编码器/校正子产生电路使用具有变化的抽头权重的单组乘法器装置来计算校验符号和误差校正子，所述抽头权重具有提供最大预选误差校正能力但容易调节的值，例如通过可编程锁存器，以从电路选择乘法器设备，以减少纠错能力，而不需要抽头重量值的变化。电路可以用于增加或减少纠错能力（a），根据在带状直接存取数据存储装置中正在访问多个记录磁道的同心磁带中的哪一个，（b）根据在数据通信信道具有受噪声的输出，或（c）根据以可变速率发送数据的发送设备的发送速率的变化。

2. 发明授权

US5270962A Multiply and divide circuit 失效
标题翻译：乘法和除法电路
公开(公告)号：US5270962A
公开(公告)日：1993-12-14
申请号：US31026
申请日：1993-03-11
申请人： Gerhard P. Fettweis
发明人： Gerhard P. Fettweis
IPC分类号： G06F7/52 , G06F7/544
CPC分类号： G06F7/5312 , G06F7/535 , G06F7/5443 , G06F2207/3836 , G06F2207/3884
摘要： A multiply and divide circuit having full bit level pipeline capability uses an array of bit level carry-save adders with each carry-save bit adder having a corresponding absolute value bit circuit. In one or two's complement notation, the carry-save adders subtract the binary values supplied thereto and generate an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary numbers supplied thereto. In one mode of operation, the circuit can be used to perform division. In another mode of operation, the circuit can be used to perform multiply and accumulate operation, again with bit level pipeline capability.
摘要翻译：具有全位电平流水线能力的乘法和除法电路使用具有相应绝对值位电路的每个进位保存位加法器的位电平进位存储加法器阵列。在一个或两个补码符号中，进位保存加法器减去提供给它的二进制值，并产生提供给绝对值电路的中间二进制信号。绝对值电路确定提供给它的二进制数的绝对值。在一种操作模式中，电路可用于执行分割。在另一种操作模式下，该电路可以用于执行乘法和累加操作，再次利用位级管道功能。

3. 发明授权

US5042036A Process for realizing the Viterbi-algorithm by means of parallel working structures 失效
标题翻译：通过平行工作结构实现维特比算法的过程
公开(公告)号：US5042036A
公开(公告)日：1991-08-20
申请号：US213166
申请日：1988-06-29
申请人： Gerhard P. Fettweis
发明人： Gerhard P. Fettweis
IPC分类号： G06F17/10 , H03M13/23 , H03M13/41
CPC分类号： H03M13/3972 , H03M13/395 , H03M13/41
摘要： A method for implementing the Viterbi algorithm (Viterbi decoder) for very high data rates/decoding rates. The trellis diagram (original trellis diagram) of the Markov process, the original trellis diagram being the basis of such implementation, is considered over a greater period. Transitions of the original trellis diagram are combined in one multi-step transition (multi-step trellis diagram) per each M. The number of transition branches, which rise exponentially, in such a process with M, is reduced to a smaller number by exploiting fundamental properties of the original trellis diagram forming the basis of the multi-step transitions. This eliminates non-optimal transition branches irrespective of the change from one multi-step transition to another. This permits the design of Viterbi decoders for very high data rates, as more time is available for executing the computing operations on number of computers as compared to the maximum permissible time for executing similar (identical) operations in the implementation of the Viterbi algorithm based on the one-step transition of the original trellis diagram.
摘要翻译：一种用于实现非常高数据速率/解码速率的维特比算法（维特比解码器）的方法。马尔可夫过程的网格图（原始网格图），原始网格图作为实施的基础，在更长的时间内被考虑。原始网格图的转换在每个M的一个多步骤转换（多步网格图）中组合。在这样一个过程中，M的转移分支数量呈指数级增长，通过开发减少到较小的数量原始网格图的基本属性形成了多步转换的基础。这消除了非最优的转移分支，而不管从一个多步骤转变到另一个步骤的变化。这允许维特比解码器的设计具有非常高的数据速率，因为与在基于维特比算法的实现中执行类似（相同）操作的最大允许时间相比，更多的时间可用于执行计算机数量的计算操作原始网格图的一步过渡。

4. 发明授权

US5442580A Parallel processing circuit and a digital signal processer including same 失效
标题翻译：并行处理电路和包括其的数字信号处理器
公开(公告)号：US5442580A
公开(公告)日：1995-08-15
申请号：US248765
申请日：1994-05-25
申请人： Gerhard P. Fettweis
发明人： Gerhard P. Fettweis
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F7/5443
摘要： A parallel processing circuit and a digital signal processor employing such a parallel circuit employs a plurality of identical multiply and accumulate (MAC) processing units. Two input signals are supplied to each of the MAC processing units. In one embodiment, a delay or a shift register delays one of the input digital signal from one MAC to another MAC. A plurality of different processed signals can be generated simultaneously based upon the supplied input digital signals, greatly increasing processing capability without increasing clock speed or increasing bandwidth access to a memory.
摘要翻译：采用这种并联电路的并行处理电路和数字信号处理器采用多个相同的乘法和累积（MAC）处理单元。两个输入信号被提供给每个MAC处理单元。在一个实施例中，延迟或移位寄存器将输入数字信号中的一个从一个MAC延迟到另一个MAC。可以基于所提供的输入数字信号同时生成多个不同的处理信号，大大增加处理能力，而不增加时钟速度或增加对存储器的带宽访问。

5. 发明授权

US5341322A Bit level pipeline divide circuit and method therefor 失效
标题翻译：位级流水线分割电路及其方法
公开(公告)号：US5341322A
公开(公告)日：1994-08-23
申请号：US881336
申请日：1992-05-11
申请人： Gerhard P. Fettweis , Herbert R. Dawid
发明人： Gerhard P. Fettweis , Herbert R. Dawid
IPC分类号： G06F7/52 , G06F7/544
CPC分类号： G06F7/5312 , G06F7/535 , G06F7/5443 , G06F2207/3836 , G06F2207/3884
摘要： A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm:Q.sub.w 1I=W-1 to 0N=N-DS=Signbit (N)Q.sub.I =S (EXOR) Q.sub.I+1N=.vertline.N.vertline.D=D/2ENDA recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.
摘要翻译：具有位电平流水线能力的分频电路使用具有相应绝对值位电平电路的每个进位存储加法器的位电平进位存储加法器阵列。在一个或两个补码符号中，进位存储加法器减去提供给它的二进制值，并产生提供给绝对值电路的中间二进制信号。绝对值电路确定提供给它的二进制数的绝对值。电路根据以下算法进行除法：Qw1 I = W-1至0 N = N-D S =信号（N）QI = S（EXOR）QI + 1 N = | N | D = D / 2 END采用进位保存加法器和绝对值位电平电路阵列的递归分频电路实现完整的管道位电平能力。

6. 发明授权

US5633897A Digital signal processor optimized for decoding a signal encoded in accordance with a Viterbi algorithm 失效
标题翻译：优化的数字信号处理器，用于对根据维特比算法编码的信号进行解码
公开(公告)号：US5633897A
公开(公告)日：1997-05-27
申请号：US558745
申请日：1995-11-16
申请人： Gerhard P. Fettweis , Mihran Touriguian
发明人： Gerhard P. Fettweis , Mihran Touriguian
IPC分类号： H03M13/41 , H04L1/00 , H03D1/00 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/41 , H03M13/4107 , H03M13/6569 , H04L1/0054
摘要： An improved DSP has two internal data buses with two MAC units each receiving data from its respective data bus. A shifter is interposed between the multiply unit and the ALU and accumulate unit. The improved DSP also has a multiplexer interposed between one of the MAC units and the two data buses. The improved DSP is optimized to decode a received digital signal encoded in accordance with the Viterbi algorithm, wherein the DSP calculates a first pair of binary signals C.sub.2n and C.sub.2n+1 a Viterbi butterfly based upon a second pair of binary C.sub.n and C.sub.n+m/2, and a transitional signal a, in accordance with: C.sub.2n =minimum (C.sub.n +a, C.sub.n+m/2 -a); C.sub.2n+1 =minimum (C.sub.n -a, C.sub.n+m/2 +a).
摘要翻译：改进的DSP具有两个内部数据总线，其中两个MAC单元各自从其相应的数据总线接收数据。移位器插在乘法单元和ALU之间并累加单元。改进的DSP还具有插入在MAC单元之一和两个数据总线之间的多路复用器。改进的DSP被优化以对根据维特比算法编码的接收数字信号进行解码，其中DSP基于第二对二进制Cn和Cn + m / 2计算第一对二进制信号C2n和C2n + 1维特比蝴蝶， 2，和过渡信号a，根据：C2n =最小（Cn + a，Cn + m / 2-a）; C2n + 1 =最小（Cn-a，Cn + m / 2 + a）。

7. 发明授权

US5602767A Galois field polynomial multiply/divide circuit and a digital signal processor incorporating same 失效
标题翻译：伽罗瓦域多项式乘法/除法电路和包含其的数字信号处理器
公开(公告)号：US5602767A
公开(公告)日：1997-02-11
申请号：US521112
申请日：1995-08-29
申请人： Gerhard P. Fettweis , Mihran Touriguian
发明人： Gerhard P. Fettweis , Mihran Touriguian
IPC分类号： G06F7/60 , G06F7/72 , G06F11/10 , H03M13/00 , H03M13/03 , H03M13/09 , H03M13/15 , G06F7/00 , G06F15/00
CPC分类号： H03M13/6569 , G06F7/726 , H03M13/033 , H03M13/09 , H03M13/151
摘要： The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.
摘要翻译：乘法/除法电路在DSP中使用ALU的异或功能。通过将移位信号回送到ALU的累加器和移位寄存器的异或功能的结果可以进行乘法或除法功能。当在DSP中用于电信目的时，乘法/除法电路可以执行卷积编码和循环冗余校验以及其他功能，具体用于电信应用。

8. 发明授权

US5430744A Method and means for detecting partial response waveforms using a modified dynamic programming heuristic 失效
标题翻译：使用修改的动态规划启发式检测部分响应波形的方法和装置
公开(公告)号：US5430744A
公开(公告)日：1995-07-04
申请号：US129904
申请日：1993-09-30
申请人： Gerhard P. Fettweis , Razmik Karabed , Paul H. Siegel , Hemant K. Thapar
发明人： Gerhard P. Fettweis , Razmik Karabed , Paul H. Siegel , Hemant K. Thapar
IPC分类号： G06F11/10 , G11B20/18 , H03M13/23 , H03M13/41 , H04L25/08 , H03M13/00 , H04L25/34 , H04L25/49
CPC分类号： H03M13/6343 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/6502
摘要： A Viterbi decoder having a recursive processor modified to process each node in a trellis of a partial response coded signal to shift the branch metric additions over the node to effectuate compare, select, add operation order on the predecessor survivor metrics terminating in that node, to compare the metrics of the predecessor sequences terminating in the node, to select a survivor sequence, and to add the shifted branch metrics to the metric of the selected survivor sequence.
摘要翻译：一种具有递归处理器的维特比解码器，其被修改为处理部分响应编码信号的网格中的每个节点，以便通过该节点移动分支度量添加，以对在该节点终止的前导幸存者度量进行比较，选择，添加操作顺序，比较终止在节点中的前导序列的度量，以选择幸存者序列，并将移位的分支度量添加到所选存活序列的度量。

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