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1. 发明授权

US08354862B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

2. 发明授权

US08179162B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

3. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

4. 发明授权

US08475039B2 Providing linear relationship between temperature and digital code 有权
标题翻译：提供温度和数字代码之间的线性关系
公开(公告)号：US08475039B2
公开(公告)日：2013-07-02
申请号：US12764532
申请日：2010-04-21
申请人： Chan-Hong Chern , Steven Swei
发明人： Chan-Hong Chern , Steven Swei
IPC分类号： G01K7/00 , H01L35/00
CPC分类号： G01K7/14 , G01K7/01 , G01K2219/00
摘要： Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code. The various temperatures experienced by the temperature sensing circuit and the DAC codes are substantially linearly related.
摘要翻译：公开了提供温度和数字代码之间的线性关系的机制。在一种方法中，在特定温度下，传感器中的电路向比较器提供与温度相关的参考电压和比较的电压。温度依赖参考电压取决于温度与绝对温度的补充，或者取决于与绝对温度成比例的温度。相应的数字模拟转换器（DAC）代码作为输入产生比较电压。另一个电路改变DAC代码，直到与温度相关的参考电压和比较的电压相等，从而相关的参考电压对应于DAC代码。温度感测电路和DAC代码经历的各种温度基本上是线性相关的。

5. 发明授权

US08183913B2 Integrated circuits including a charge pump circuit and operating methods thereof 有权
标题翻译：包括电荷泵电路的集成电路及其操作方法
公开(公告)号：US08183913B2
公开(公告)日：2012-05-22
申请号：US12706886
申请日：2010-02-17
申请人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

6. 发明授权

US08575966B2 Method of operating phase-lock assistant circuitry 有权
标题翻译：操作锁相辅助电路的方法
公开(公告)号：US08575966B2
公开(公告)日：2013-11-05
申请号：US13718235
申请日：2012-12-18
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.
摘要翻译：操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。电荷泵电路根据上升信号和下降信号进行驱动。

7. 发明授权

US09524934B2 Integrated circuits with electrical fuses and methods of forming the same 有权
标题翻译：具有电熔丝的集成电路及其形成方法
公开(公告)号：US09524934B2
公开(公告)日：2016-12-20
申请号：US13302335
申请日：2011-11-22
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Kuoyuan (Peter) Hsu
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Kuoyuan (Peter) Hsu
IPC分类号： H01L21/8238 , H01L23/525 , H01L27/06 , H01L29/51 , H01L29/66
CPC分类号： H01L23/5256 , H01L21/823437 , H01L27/0617 , H01L27/0629 , H01L27/11206 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
摘要翻译：形成集成电路的方法包括在衬底上形成至少一个晶体管。形成至少一个晶体管包括在衬底上形成栅极电介质结构。在栅介电结构上形成功函数金属层。在功函数金属层上形成导电层。源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。在衬底上形成至少一个电熔丝。形成至少一个电熔丝包括在衬底上形成第一半导体层。在第一半导体层上形成第一硅化物层。

8. 发明授权

US08884665B2 Multiple-phase clock generator 有权
标题翻译：多相时钟发生器
公开(公告)号：US08884665B2
公开(公告)日：2014-11-11
申请号：US13084817
申请日：2011-04-12
申请人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
发明人： Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang , Tao Wen Chung
IPC分类号： H03B19/00 , H03K5/15
CPC分类号： H03K5/15013
摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.
摘要翻译：多相时钟发生器包括至少一个分频器级。时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。第N级包括2N个分频器，其中N是正整数。第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

9. 发明授权

US08872592B2 High-speed transimpedance amplifier 有权
标题翻译：高速互阻放大器
公开(公告)号：US08872592B2
公开(公告)日：2014-10-28
申请号：US13527365
申请日：2012-06-19
申请人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
发明人： Tsung-Ching Huang , Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03F3/08
CPC分类号： H03F3/082 , H03F1/0205 , H03F3/08 , H03F3/3022 , H03F3/45179 , H03F3/45183 , H03F2200/216 , H03F2203/30031 , H03F2203/45222 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702 , H03F2203/45724
摘要： A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node.
摘要翻译：跨阻放大器包括具有第一输入节点和第一输出节点的第一反相器。第一输入节点被配置为耦合到输入信号。第二反相器具有第二输入节点和第二输出节点。第二输入节点被配置为接收参考电压端子。第一反相器和第二反相器被配置为在第一输出节点和第二输出节点之间提供差分输出电压信号。

10. 发明授权

US08862951B2 Decision feedback equalizer 有权
标题翻译：决策反馈均衡器
公开(公告)号：US08862951B2
公开(公告)日：2014-10-14
申请号：US13528877
申请日：2012-06-21
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Yuwen Swei , Chih-Chang Lin , Tsung-Ching Huang
IPC分类号： G06F11/00 , H04L27/01
CPC分类号： H04L25/03057 , H04L25/06 , H04L25/08
摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
摘要翻译：电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号由第一求和电路接收。第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号由第一求和电路接收。

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