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1. 发明申请

US20060024905A1 Metal capacitor stacked with a MOS capacitor to provide increased capacitance density 有权
标题翻译：金属电容器堆叠有MOS电容器以提供增加的电容密度
公开(公告)号：US20060024905A1
公开(公告)日：2006-02-02
申请号：US10903938
申请日：2004-07-30
申请人： Canzhong He , John Schuler , John Sharpe , Hong-Ha Vuong
发明人： Canzhong He , John Schuler , John Sharpe , Hong-Ha Vuong
IPC分类号： H01L21/20
CPC分类号： H01L28/86 , H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.
摘要翻译：片上电容器件包括半导体衬底，形成在半导体衬底上的MOS电容器和至少部分地形成在MOS电容器上方的金属互连电容器。 MOS电容器和金属互连电容器并联连接以形成单个电容器件。因此，MOS电容器和金属互连电容器的电容密度被组合。有利地，可以在没有额外的处理步骤的情况下实现显着的电容密度增益。

2. 发明授权

US07768044B2 Metal capacitor stacked with a MOS capacitor to provide increased capacitance density 有权
标题翻译：金属电容器堆叠有MOS电容器以提供增加的电容密度
公开(公告)号：US07768044B2
公开(公告)日：2010-08-03
申请号：US10903938
申请日：2004-07-30
申请人： Canzhong He , John A. Schuler , John M. Sharpe , Hong-Ha Vuong
发明人： Canzhong He , John A. Schuler , John M. Sharpe , Hong-Ha Vuong
IPC分类号： H01L29/76 , H01L29/94 , H01L21/20 , H01L21/336 , H01L21/8234
CPC分类号： H01L28/86 , H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.
摘要翻译：片上电容器件包括半导体衬底，形成在半导体衬底上的MOS电容器和至少部分地形成在MOS电容器上方的金属互连电容器。 MOS电容器和金属互连电容器并联连接以形成单个电容器件。因此，MOS电容器和金属互连电容器的电容密度被组合。有利地，可以在没有额外的处理步骤的情况下实现显着的电容密度增益。

3. 发明授权

US08464202B2 Fully parameterizable representation of a higher level design entity 有权
标题翻译：高级设计实体的全参数化表示
公开(公告)号：US08464202B2
公开(公告)日：2013-06-11
申请号：US13114834
申请日：2011-05-24
申请人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-Ha Vuong
发明人： Shawn Boshart , Shahriar Moinian , Joshua Williams , Hong-Ha Vuong
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5063 , G06F2217/66
摘要： A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.
摘要翻译：可参数化的设计系统与半导体模拟电路一起使用，并且包括被连接以提供对系统的访问的接口单元，连接到用于为设计实体提供可参数化的模拟构建块的库的数据库单元，以及连接以选择一个参数为可参数化的模拟构建块之一，以满足设计实体的设计规范。此外，可参数化设计系统还可以包括连接以模拟使用参数的设计实体的操作的模拟单元，以及连接以基于设计规范分析设计实体的参数的灵敏度的分析器单元。还包括设计半导体模拟电路的方法。

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