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1. 发明申请

US20110233636A1 Semiconductor Memory Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110233636A1
公开(公告)日：2011-09-29
申请号：US13050320
申请日：2011-03-17
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的方法。非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

2. 发明申请

US20110233610A1 Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions 有权
标题翻译：具有存储单元晶体管的非易失性存储器件具有较低的带隙源/漏区
公开(公告)号：US20110233610A1
公开(公告)日：2011-09-29
申请号：US12974542
申请日：2010-12-21
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/772
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.
摘要翻译：非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。源极/漏极区域可以与沟道区域形成非整流结。源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

3. 发明授权

US08441062B2 Nonvolatile memory devices having memory cell transistors therein with lower bandgap source/drain regions 有权
标题翻译：具有其中具有较低带隙源极/漏极区域的存储单元晶体管的非易失性存储器件
公开(公告)号：US08441062B2
公开(公告)日：2013-05-14
申请号：US12974542
申请日：2010-12-21
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/772
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.
摘要翻译：非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。源极/漏极区域可以与沟道区域形成非整流结。源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

4. 发明授权

US08134873B2 Flash memory device and programming/erasing method of the same 有权
标题翻译：闪存设备和编程/擦除方法相同
公开(公告)号：US08134873B2
公开(公告)日：2012-03-13
申请号：US12591428
申请日：2009-11-19
申请人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
发明人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10
摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.
摘要翻译：闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线，控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

5. 发明申请

US20060022276A1 Methods of forming semiconductor devices including a resistor in a resistor region and devices so formed 审中-公开
标题翻译：在电阻器区域中形成包括电阻器的半导体器件的形成方法和如此形成的器件
公开(公告)号：US20060022276A1
公开(公告)日：2006-02-02
申请号：US11023892
申请日：2004-12-28
申请人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
发明人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11531 , H01L28/20
摘要： Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices are also disclosed.
摘要翻译：形成半导体器件的方法可以包括在器件的衬底上形成栅电极的第一导电层，并且在与第一导电层隔开的衬底上形成与第一导电层不同的电阻器的第二导电层栅电极。还公开了相关设备。

6. 发明申请

US20090321815A1 Non-volatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090321815A1
公开(公告)日：2009-12-31
申请号：US12453035
申请日：2009-04-28
申请人： Suk-kang Sung , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur
发明人： Suk-kang Sung , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur
IPC分类号： H01L29/792 , H01L27/092
CPC分类号： H01L21/823493 , H01L21/823456 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.
摘要翻译：一种非易失性存储器件，包括第一导电类型的衬底，所述衬底包括多个第二导电类型的阱，多个第二导电类型的阱之一中的多个存储单元，以及周边包括至少一个第一导电类型的第一晶体管和第二导电类型的另一个第二导电类型的第二导体类型的第二晶体管。

7. 发明申请

US20100128522A1 Flash memory device and programming/erasing method of the same 有权
标题翻译：闪存设备和编程/擦除方法相同
公开(公告)号：US20100128522A1
公开(公告)日：2010-05-27
申请号：US12591428
申请日：2009-11-19
申请人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
发明人： Dong-uk Choi , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur , Min-tai Yu
IPC分类号： G11C16/16 , G11C16/04 , G11C16/12
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10
摘要： A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.
摘要翻译：闪速存储器件包括体区域，在体区域上排列成行的第一至第n个存储单元晶体管，分别连接到第一至第n存储单元晶体管的栅极的第一至第n字线，连接到第一存储单元晶体管，连接到第一虚设单元晶体管的栅极的第一虚拟字线，连接到第一虚设单元晶体管的第一选择晶体管，连接到第一选择晶体管的栅极的第一选择线，控制单元连接到第一选择线，电压控制单元适于在以擦除第一至第n个存储单元晶体管的擦除模式中向第一选择线输出低于施加到体区的电压的电压。

8. 发明授权

US08018781B2 Method of operating nonvolatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US08018781B2
公开(公告)日：2011-09-13
申请号：US12071960
申请日：2008-02-28
申请人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
发明人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.
摘要翻译：提供了一种操作非易失性存储器件以执行擦除操作的方法。该方法包括将包括直流（DC）脉冲和DC扰动脉冲的复合脉冲施加到非易失性存储器件以执行擦除操作。

9. 发明申请

US20080205156A1 Method of operating nonvolatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US20080205156A1
公开(公告)日：2008-08-28
申请号：US12071960
申请日：2008-02-28
申请人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
发明人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.
摘要翻译：提供了一种操作非易失性存储器件以执行擦除操作的方法。该方法包括将包括直流（DC）脉冲和DC扰动脉冲的复合脉冲施加到非易失性存储器件以执行擦除操作。

10. 发明授权

US09564435B2 Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device 有权
标题翻译：包括具有不同栅极结构的FinFET和半导体器件的制造方法的半导体器件
公开(公告)号：US09564435B2
公开(公告)日：2017-02-07
申请号：US14754400
申请日：2015-06-29
申请人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
发明人： Eun-ae Chung , Jung-dal Choi , Toshiro Nakanishi , Yu-bin Kim , Gab-jin Nam , Dong-kyu Lee , Guangfan Jiao
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L27/088 , H01L21/8234
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L27/1211
摘要： A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.
摘要翻译：半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。第一和第二栅极电介质层具有不同的厚度。还讨论了相关设备和制造方法。

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