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1. 发明申请

US20070180423A1 Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights 有权
标题翻译：用于指定利用拨盘偏置权重的数字系统的配置的方法，系统和程序产品
公开(公告)号：US20070180423A1
公开(公告)日：2007-08-02
申请号：US11345847
申请日：2006-02-02
申请人： Bryan Hunt , Wolfgang Roesner , Robert Shadowen , Derek Williams
发明人： Bryan Hunt , Wolfgang Roesner , Robert Shadowen , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity.
摘要翻译：在数据处理的方法中，数据库定义了Dial实体和Dial实体的至少一个实例。 Dial实体的每个实例具有具有多个不同可能输入值和一个或多个输出的输入，并且多个不同可能输入值中的每一个具有为一个或多个输出设置的不同的相关输出值。 Dial实体的每个实例确定与数据库分离的数字系统中的多个配置锁存器中的至少一个的值。所述数据库还将所述至少一组偏置权重与所述拨号实体相关联，所述偏置权重在被应用时确定具有所述多个不同可能输入值中的特定个体的所述拨号实体的每个实例的概率。响应于设置多个配置锁存器的呼叫，访问数据库以应用至少一组偏置权重以选择Dial实体的至少一个实例的多个不同可能输入值中的一个。基于为Dial实体的至少一个实例的一个或多个输出设置的输出值来设置数字系统中的多个配置锁存器。

2. 发明申请

US20070083843A1 Method, system and program product for providing a configuration specification language supporting error checking dials 失效
标题翻译：方法，系统和程序产品，用于提供支持错误检查拨盘的配置说明语言
公开(公告)号：US20070083843A1
公开(公告)日：2007-04-12
申请号：US11245300
申请日：2005-10-06
申请人： Wolfgang Roesner , Robert Shadowen , Derek Williams
发明人： Wolfgang Roesner , Robert Shadowen , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated. The configuration entities including an Error checking Dial (EDial) having a plurality of input latches within the digital design and a plurality of output latches within the digital design. The EDial has an associated function defining a relationship between values of the input latches and values of the output latches. An instance of the EDial in the configuration database is accessed to access the values of the output latches in the digital design.
摘要翻译：数字系统包括包含数字系统的功能部分的一个或多个设计实体。在配置数据库中，一个或多个配置实体被实例化。配置实体包括在数字设计中具有多个输入锁存器的错误检查拨号（EDial）和数字设计中的多个输出锁存器。 EDial具有定义输入锁存器的值和输出锁存器值之间的关系的相关函数。访问配置数据库中的EDial实例以访问数字设计中输出锁存器的值。

3. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

4. 发明申请

US20060291295A1 Method, system and program product for configuring a digital system based upon system-level variables 审中-公开
标题翻译：基于系统级变量配置数字系统的方法，系统和程序产品
公开(公告)号：US20060291295A1
公开(公告)日：2006-12-28
申请号：US11143329
申请日：2005-06-02
申请人： Sauniell Connally , Astrid Kreissig , Robert Shadowen , Matthew Spinler
发明人： Sauniell Connally , Astrid Kreissig , Robert Shadowen , Matthew Spinler
IPC分类号： G11C7/00
CPC分类号： G06F17/5045
摘要： In a method of data processing, a binary system configuration file is interpreted by reference to a value set of at least one system-level variable in response to a configuration event. The binary system configuration file contains a binary representation of a plurality of system configuration statements specifying a plurality of different alternative configurations of a data processing system in terms of the at least one system-level variable. In response to interpreting the binary system configuration file, the data processing system is configured for operation by setting one or more configuration latches within the data processing system.
摘要翻译：在数据处理的方法中，响应于配置事件，参考至少一个系统级变量的值集解释二进制系统配置文件。所述二进制系统配置文件包含多个系统配置语句的二进制表示，所述多个系统配置语句根据所述至少一个系统级变量指定数据处理系统的多个不同替代配置。响应于解释二进制系统配置文件，数据处理系统被配置为通过在数据处理系统内设置一个或多个配置锁存器来进行操作。

5. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

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