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1. 发明申请

US20100277219A1 Clock Gater with Test Features and Low Setup Time 有权
标题翻译：具有测试功能和低设置时间的时钟控制器
公开(公告)号：US20100277219A1
公开(公告)日：2010-11-04
申请号：US12836141
申请日：2010-07-14
申请人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
发明人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
IPC分类号： H03K17/687
CPC分类号： H03K19/0016 , G01R31/31922 , G06F1/10 , G06F1/3237 , H03K17/687 , Y02D10/128
摘要： A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.
摘要翻译：时钟门电路包括多个具有在第一节点和供电节点之间形成堆叠的源极 - 漏极连接的晶体管。第一节点上的给定逻辑状态在时钟门控电路的输出时钟上引起相应的逻辑状态。在一个实施例中，多个晶体管中的第一晶体管具有耦合以接收使能输入信号的栅极。第二晶体管与第一晶体管并联连接，并且响应于测试输入信号具有控制门，以确保即使使能输入信号不处于使能状态也能产生输出时钟。在另一个实施例中，多个晶体管包括响应于时钟门电路电路的时钟输入的门控制的第一晶体管和响应于延迟电路的输出的具有门控制的第二晶体管。所述延迟电路包括至少一个逆变器，其中所述延迟电路的输入是所述时钟输入，并且其中所述延迟电路的第一反相器被耦合以接收测试输入信号，并且被配置为在输出端上强制第一逻辑状态所述第一逆变器响应于所述测试输入信号的断言。

2. 发明申请

US20080180159A1 Clock Gater with Test Features and Low Setup Time 有权
标题翻译：具有测试功能和低设置时间的时钟控制器
公开(公告)号：US20080180159A1
公开(公告)日：2008-07-31
申请号：US11627646
申请日：2007-01-26
申请人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
发明人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
IPC分类号： H03K17/687
CPC分类号： H03K19/0016 , G01R31/31922 , G06F1/10 , G06F1/3237 , H03K17/687 , Y02D10/128
摘要： A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.
摘要翻译：时钟门电路包括多个具有在第一节点和供电节点之间形成堆叠的源极 - 漏极连接的晶体管。第一节点上的给定逻辑状态在时钟门控电路的输出时钟上引起相应的逻辑状态。在一个实施例中，多个晶体管中的第一晶体管具有耦合以接收使能输入信号的栅极。第二晶体管与第一晶体管并联连接，并且响应于测试输入信号具有控制门，以确保即使使能输入信号不处于使能状态也能产生输出时钟。在另一个实施例中，多个晶体管包括响应于时钟门电路电路的时钟输入的门控制的第一晶体管和响应于延迟电路的输出的具有门控制的第二晶体管。所述延迟电路包括至少一个逆变器，其中所述延迟电路的输入是所述时钟输入，并且其中所述延迟电路的第一反相器被耦合以接收测试输入信号，并且被配置为在输出端上强制第一逻辑状态所述第一逆变器响应于所述测试输入信号的断言。

3. 发明授权

US07779372B2 Clock gater with test features and low setup time 有权
标题翻译：时钟门控器具有测试功能和低设置时间
公开(公告)号：US07779372B2
公开(公告)日：2010-08-17
申请号：US11627646
申请日：2007-01-26
申请人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
发明人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
IPC分类号： G06F17/50
CPC分类号： H03K19/0016 , G01R31/31922 , G06F1/10 , G06F1/3237 , H03K17/687 , Y02D10/128
摘要： A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.
摘要翻译：时钟门电路包括多个具有在第一节点和供电节点之间形成堆叠的源极 - 漏极连接的晶体管。第一节点上的给定逻辑状态在时钟门控电路的输出时钟上引起相应的逻辑状态。在一个实施例中，多个晶体管中的第一晶体管具有耦合以接收使能输入信号的栅极。第二晶体管与第一晶体管并联连接，并且响应于测试输入信号具有控制门，以确保即使使能输入信号不处于使能状态也能产生输出时钟。在另一个实施例中，多个晶体管包括响应于时钟门电路电路的时钟输入的门控制的第一晶体管和响应于延迟电路的输出的具有门控制的第二晶体管。所述延迟电路包括至少一个逆变器，其中所述延迟电路的输入是所述时钟输入，并且其中所述延迟电路的第一反相器被耦合以接收测试输入信号，并且被配置为在输出端上强制第一逻辑状态所述第一逆变器响应于所述测试输入信号的断言。

4. 发明授权

US08341578B2 Clock gater with test features and low setup time 有权
标题翻译：时钟门控器具有测试功能和低设置时间
公开(公告)号：US08341578B2
公开(公告)日：2012-12-25
申请号：US12836141
申请日：2010-07-14
申请人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
发明人： Brian J. Campbell , Shaishav Desai , Edgardo F. Klass , Pradeep R. Trivedi , Sridhar Narayanan
IPC分类号： G06F17/50
CPC分类号： H03K19/0016 , G01R31/31922 , G06F1/10 , G06F1/3237 , H03K17/687 , Y02D10/128
摘要： A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.
摘要翻译：时钟门电路包括多个具有在第一节点和供电节点之间形成堆叠的源极 - 漏极连接的晶体管。第一节点上的给定逻辑状态在时钟门控电路的输出时钟上引起相应的逻辑状态。在一个实施例中，多个晶体管中的第一晶体管具有耦合以接收使能输入信号的栅极。第二晶体管与第一晶体管并联连接，并且响应于测试输入信号具有控制门，以确保即使使能输入信号不处于使能状态也能产生输出时钟。在另一个实施例中，多个晶体管包括响应于时钟门电路电路的时钟输入的门控制的第一晶体管和响应于延迟电路的输出的具有门控制的第二晶体管。所述延迟电路包括至少一个逆变器，其中所述延迟电路的输入是所述时钟输入，并且其中所述延迟电路的第一反相器被耦合以接收测试输入信号，并且被配置为在输出端上强制第一逻辑状态所述第一逆变器响应于所述测试输入信号的断言。

5. 发明授权

US08416635B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
公开(公告)号：US08416635B2
公开(公告)日：2013-04-09
申请号：US13617344
申请日：2012-09-14
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

6. 发明申请

US20130016575A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20130016575A1
公开(公告)日：2013-01-17
申请号：US13617344
申请日：2012-09-14
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

7. 发明授权

US08171326B2 L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down 有权
标题翻译： L1冲洗机构刷新缓存以断电并处理冲水和/或断电后的一致性
公开(公告)号：US08171326B2
公开(公告)日：2012-05-01
申请号：US12785842
申请日：2010-05-24
申请人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
发明人： James B. Keller , Tse-Yu Yeh , Ramesh Gunna , Brian J. Campbell
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a processor comprises a data cache configured to store a plurality of cache blocks and a control unit coupled to the data cache. The control unit is configured to flush the plurality of cache blocks from the data cache responsive to an indication that the processor is to transition to a low power state in which one or more clocks for the processor are inhibited.
摘要翻译：在一个实施例中，处理器包括被配置为存储多个高速缓存块的数据高速缓存和耦合到数据高速缓存的控制单元。控制单元被配置为响应于处理器将转换到其中禁止用于处理器的一个或多个时钟的低功率状态的指示，从数据高速缓冲存储器中刷新多个高速缓存块。

8. 发明授权

US08102728B2 Cache optimizations using multiple threshold voltage transistors 有权
标题翻译：使用多个阈值电压晶体管的缓存优化
公开(公告)号：US08102728B2
公开(公告)日：2012-01-24
申请号：US12419605
申请日：2009-04-07
申请人： Brian J. Campbell , Greg M. Hess , Hang Huang
发明人： Brian J. Campbell , Greg M. Hess , Hang Huang
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C8/08 , G11C11/417
摘要： In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.
摘要翻译：在一个实施例中，存储器电路包括一个或多个存储单元，其包括具有第一标称阈值电压的晶体管，以及诸如字线驱动器和位线控制电路的接口电路，其包括具有第二标称阈值电压的一个或多个晶体管，低于第一标称阈值电压。例如，字线驱动器电路可以由比存储器电路的电压域更低的电压域的信号来驱动。在一些实施例中，下阈值电压晶体管可用于那些信号。类似地，在写入数据驱动器电路中可以使用较低阈值电压晶体管。其它位线控制电路可以包括较低阈值电压晶体管，以允许使用更小的晶体管，这可以降低由存储器电路占用的功率和集成电路面积。

9. 发明授权

US08098534B2 Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage 有权
标题翻译：具有不同于逻辑电路电源电压的存储器的单独电源电压的集成电路
公开(公告)号：US08098534B2
公开(公告)日：2012-01-17
申请号：US12791080
申请日：2010-06-01
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供有在使用期间大于所述第一电源电压的第二电源电压。

10. 发明申请

US20110235442A1 Integrated Circuit with Separate Supply Voltage for Memory That is Different from Logic Circuit Supply Voltage 有权
标题翻译：具有与逻辑电路电源电压不同的存储器的独立电源电压的集成电路
公开(公告)号：US20110235442A1
公开(公告)日：2011-09-29
申请号：US13155097
申请日：2011-06-07
申请人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.
摘要翻译：在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

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