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1. 发明授权

US08304262B2 Wiggling control for pseudo-hardmask 有权
标题翻译：伪硬掩码的摆动控制
公开(公告)号：US08304262B2
公开(公告)日：2012-11-06
申请号：US13029824
申请日：2011-02-17
申请人： Ben-Li Sheu , Rajinder Dhindsa , Vinay Pohray , Eric A. Hudson , Andrew D. Bailey, III
发明人： Ben-Li Sheu , Rajinder Dhindsa , Vinay Pohray , Eric A. Hudson , Andrew D. Bailey, III
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/461 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/31144
摘要： A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.
摘要翻译：一种用于蚀刻蚀刻层中的特征的方法。提供了一种用于设置在蚀刻层上的非晶碳或多晶硅的图案化伪硬掩模的调理，其中调节包括提供包含烃气体的无氟沉积气体，从无氟沉积气体形成等离子体，超过500伏，并且在图案化伪硬掩模的顶部上形成沉积物。蚀刻层通过图案化伪硬掩模进行蚀刻。

2. 发明申请

US20120214310A1 WIGGLING CONTROL FOR PSEUDO-HARDMASK 有权
标题翻译： PSEUDO-HARDMASK的激光控制
公开(公告)号：US20120214310A1
公开(公告)日：2012-08-23
申请号：US13029824
申请日：2011-02-17
申请人： Ben-Li Sheu , Rajinder Dhindsa , Vinay Pohray , Eric A. Husdon , Andrew D. Bailey, III
发明人： Ben-Li Sheu , Rajinder Dhindsa , Vinay Pohray , Eric A. Husdon , Andrew D. Bailey, III
IPC分类号： H01L21/311 , C23F1/08
CPC分类号： H01L21/31116 , H01L21/31144
摘要： A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.
摘要翻译：一种用于蚀刻蚀刻层中的特征的方法。提供了一种用于设置在蚀刻层上的非晶碳或多晶硅的图案化伪硬掩模的调理，其中调节包括提供包含烃气体的无氟沉积气体，从无氟沉积气体形成等离子体，超过500伏，并且在图案化伪硬掩模的顶部上形成沉积物。蚀刻层通过图案化伪硬掩模进行蚀刻。

3. 发明授权

US06794293B2 Trench etch process for low-k dielectrics 有权
标题翻译：低k电介质的沟槽蚀刻工艺
公开(公告)号：US06794293B2
公开(公告)日：2004-09-21
申请号：US09972765
申请日：2001-10-05
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
摘要翻译：本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。优选地，该方法用于不具有中间蚀刻停止层的低k电介质。另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

4. 发明授权

US07307025B1 Lag control 有权
标题翻译：滞后控制
公开(公告)号：US07307025B1
公开(公告)日：2007-12-11
申请号：US11104733
申请日：2005-04-12
申请人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
发明人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31138
摘要： A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.
摘要翻译：一种用于在衬底上蚀刻基于氧化硅的电介质层中的特征的方法，包括执行蚀刻循环。执行基于氧化硅的电介质层中部分蚀刻部分蚀刻特征的延迟蚀刻，包括提供滞后的蚀刻剂气体，从滞后的蚀刻剂气体形成等离子体，并用滞后的蚀刻剂气体蚀刻蚀刻层，使得较小的特征被蚀刻更慢比更广泛的功能。执行反向延迟蚀刻进一步蚀刻基于氧化硅的电介质层中的特征，其包括提供与滞后蚀刻剂气体不同的反向滞后蚀刻剂气体，并且比滞后蚀刻剂气体更聚合，从逆向滞后形成等离子体蚀刻气体，并用由反向滞后蚀刻剂气体形成的等离子体蚀刻基于氧化硅的电介质层，从而比较宽的特征蚀刻更小的特征。

5. 发明授权

US06875699B1 Method for patterning multilevel interconnects 有权
标题翻译：图形化多层互连的方法
公开(公告)号：US06875699B1
公开(公告)日：2005-04-05
申请号：US10138041
申请日：2002-05-01
申请人： Stephan Lassig , S. M. Reza Sadjadi , Vinay Pohray , Si Yi Li , Thomas W. Mountsier , Chiu Chi
发明人： Stephan Lassig , S. M. Reza Sadjadi , Vinay Pohray , Si Yi Li , Thomas W. Mountsier , Chiu Chi
IPC分类号： G03F7/09 , H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/302
CPC分类号： H01L21/02063 , G03F7/091 , H01L21/31116 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76808 , H01L21/76829
摘要： A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.
摘要翻译：提供了一种在衬底上形成镶嵌结构的方法。低k电介质层形成在衬底上，其中低k电介质层不具有沟槽停止层。通过低k电介质层蚀刻多个通孔。通过插塞形成在多个通孔中。多个沟槽被蚀刻到低k电介质层中，其中具有足够高的通孔插塞的蚀刻最小化暴露于蚀刻的通孔顶部的小面形成，并且其中沟槽蚀刻工艺移除由通孔插塞引起的栅栏。通孔塞被剥去。

6. 发明授权

US07789991B1 Lag control 有权
标题翻译：滞后控制
公开(公告)号：US07789991B1
公开(公告)日：2010-09-07
申请号：US11810929
申请日：2007-06-07
申请人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
发明人： Binet A. Worsham , Sean S. Kang , David Wei , Vinay Pohray , Bi Ming Yen
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01L21/31116 , H01L21/31138
摘要： A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.
摘要翻译：一种用于在衬底上蚀刻基于氧化硅的电介质层中的特征的方法，包括执行蚀刻循环。执行基于氧化硅的电介质层中部分蚀刻部分蚀刻特征的延迟蚀刻，包括提供滞后的蚀刻剂气体，从滞后的蚀刻剂气体形成等离子体，并用滞后的蚀刻剂气体蚀刻蚀刻层，使得较小的特征被蚀刻更慢比更广泛的功能。执行反向延迟蚀刻进一步蚀刻基于氧化硅的电介质层中的特征，其包括提供与滞后蚀刻剂气体不同的反向滞后蚀刻剂气体，并且比滞后蚀刻剂气体更聚合，从逆向滞后形成等离子体蚀刻气体，并用由反向滞后蚀刻剂气体形成的等离子体蚀刻基于氧化硅的电介质层，从而比较宽的特征蚀刻更小的特征。

7. 发明授权

US06909195B2 Trench etch process for low-k dielectrics 有权
公开(公告)号：US06909195B2
公开(公告)日：2005-06-21
申请号：US10826211
申请日：2004-04-16
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L23/48
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

8. 发明申请

US20050009324A1 Trench etch process for low-k dielectrics 有权
标题翻译：低k电介质的沟槽蚀刻工艺
公开(公告)号：US20050009324A1
公开(公告)日：2005-01-13
申请号：US10826211
申请日：2004-04-16
申请人： SiYi Li , S.M. Sadjadi , David Pirkle , Stephan Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S.M. Sadjadi , David Pirkle , Stephan Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21/311 , H01L21/312 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
摘要翻译：本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。优选地，该方法用于不具有中间蚀刻停止层的低k电介质。另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

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