专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070228514A1 Electronic Device 有权
标题翻译：电子设备
公开(公告)号：US20070228514A1
公开(公告)日：2007-10-04
申请号：US11579679
申请日：2005-05-03
申请人： Arnoldus Den Dekker , Johannes Dijkhuis , Nicolas Pulsford , Jozef Van Beek , Freddy Roozeboom , Antonius Lucien Kemmeren , Johan Klootwijk , Maarten Nollen
发明人： Arnoldus Den Dekker , Johannes Dijkhuis , Nicolas Pulsford , Jozef Van Beek , Freddy Roozeboom , Antonius Lucien Kemmeren , Johan Klootwijk , Maarten Nollen
IPC分类号： H01L27/00
CPC分类号： H03H3/00 , H03H7/0123
摘要： The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.
摘要翻译：电子器件包括至少一个薄膜电容器的网络和在半导体材料的衬底的第一侧上的至少一个电感器。衬底具有足够高的电阻以限制电感器的电损耗，并且在其第一侧上设置有电绝缘表面层。在衬底中限定第一和第二横向pin二极管，每个pin二极管具有掺杂p区，掺杂n区和中间固有区。第一pin二极管的本征区域大于第二pin二极管的本征区域。

2. 发明申请

US20100006996A1 CARRIER FOR BONDING A SEMICONDUCTOR SHIP ONTO AND A METHOD OF CONTRACTING A SEMICONDUCTOR CHIP TO A CARRIER 有权
标题翻译：用于连接半导体船的载体和将半导体芯片合并到载体的方法
公开(公告)号：US20100006996A1
公开(公告)日：2010-01-14
申请号：US12526619
申请日：2008-02-11
申请人： Klaas Heres , Paul Dijkstra , Maarten Nollen
发明人： Klaas Heres , Paul Dijkstra , Maarten Nollen
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/3121 , H01L21/4832 , H01L23/49531 , H01L23/49575 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/92247 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H05K3/244 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.
摘要翻译：提供一种用于将半导体芯片（114）接合到其上的载体（100），其中所述载体（100）包括芯片焊盘（101）和多个接触焊盘（102），其中所述多个接触焊盘）包括导电多层堆叠，其中所述导电多层堆叠包括表面层（109），第一缓冲层和第一导电层（108）。此外，第一缓冲层包括适于防止表面层（109）的材料扩散到第一导电层（108）中的材料，并且至少两个接触焊盘（102）相对于彼此具有超细间距。

3. 发明授权

US07989934B2 Carrier for bonding a semiconductor chip onto and a method of contracting a semiconductor chip to a carrier 有权
标题翻译：用于将半导体芯片接合的载体和将半导体芯片收缩到载体的方法
公开(公告)号：US07989934B2
公开(公告)日：2011-08-02
申请号：US12526619
申请日：2008-02-11
申请人： Klaas Heres , Paul Dijkstra , Maarten Nollen
发明人： Klaas Heres , Paul Dijkstra , Maarten Nollen
IPC分类号： H01L23/495
CPC分类号： H01L23/3121 , H01L21/4832 , H01L23/49531 , H01L23/49575 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/92247 , H01L2924/00014 , H01L2924/01046 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H05K3/244 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A carrier (100) for bonding a semiconductor chip (114) onto is provided, wherein the carrier (100) comprises a die pad (101) and a plurality of contact pads (102), wherein each of the plurality of contact pads (102) comprises an electrically conductive multilayer stack, wherein the electrically conductive multilayer stack comprises a surface layer (109), a first buffer layer, and a first conductive layer (108). Furthermore, the first buffer layer comprises a material adapted to prevent diffusion of material of the surface layer (109) into the first conductive layer (108), and at least two of the contact pads (102) has an ultrafine pitch relative to each other.
摘要翻译：提供一种用于将半导体芯片（114）接合到其上的载体（100），其中所述载体（100）包括芯片焊盘（101）和多个接触焊盘（102），其中所述多个接触焊盘）包括导电多层堆叠，其中所述导电多层堆叠包括表面层（109），第一缓冲层和第一导电层（108）。此外，第一缓冲层包括适于防止表面层（109）的材料扩散到第一导电层（108）中的材料，并且至少两个接触焊盘（102）相对于彼此具有超细间距。

4. 发明申请

US20080006684A1 Security Paper an Darticles Comprising Such Paper 审中-公开
标题翻译：安全论文包含这样的论文
公开(公告)号：US20080006684A1
公开(公告)日：2008-01-10
申请号：US11571579
申请日：2005-07-12
申请人： Maarten Nollen
发明人： Maarten Nollen
IPC分类号： G06F17/00
CPC分类号： G07D7/01
摘要： The currency note (10) is provided with a first and a second integrated circuit (1,3), that each have an antenna (2,4). The antennas (2,4) preferably operate at different frequencies. Each of the integrated circuits (2,4) comprises a memory in which a chip code and a combination code are stored. The combination code has been programmed only after integration of the integrated circuits (2,4) into the currency note (10), and allows the recognition that the first integrated circuit (1) is part of the same currency note (10) as the second integrated circuit (3), when a plurality of currency notes (10) is read out at once, wirelessly.
摘要翻译：钞票（10）设置有第一和第二集成电路（1,3），每个具有天线（2,4）。天线（2,4）优选地以不同的频率操作。集成电路（2,4）中的每一个包括存储芯片代码和组合代码的存储器。组合代码仅在将集成电路（2,4）集成到货币单（10）中之后才被编程，并且允许识别第一集成电路（1）是与第一集成电路（10）相同的货币单元（10）的一部分，第二集成电路（3），当多个钞票（10）被无线地一次读出时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式