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1. 发明申请

US20180225216A1 DATA PROCESSING 审中-公开
公开(公告)号：US20180225216A1
公开(公告)日：2018-08-09
申请号：US15427421
申请日：2017-02-08
申请人： ARM Limited
发明人： Michael FILIPPO , Jamshed JALAL , Klas Magnus BRUCE , Alex James WAUGH , Geoffray LACOURBA , Paul Gilbert MEYER , Bruce James MATHEWSON , Phanindra Kumar MANNAVA
IPC分类号： G06F12/0862 , G06F15/78
CPC分类号： G06F12/0862 , G06F11/34 , G06F12/0811 , G06F12/0833 , G06F15/7825 , G06F2212/502 , G06F2212/507
摘要： Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

2. 发明申请

US20180225214A1 CACHE CONTENT MANAGEMENT 审中-公开
公开(公告)号：US20180225214A1
公开(公告)日：2018-08-09
申请号：US15427459
申请日：2017-02-08
申请人： ARM Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Jamshed JALAL , Klas Magnus BRUCE , Michael FILIPPO , Paul Gilbert MEYER , Alex James WAUGH , Geoffray Matthieu LACOURBA
IPC分类号： G06F12/0831 , G06F9/46
CPC分类号： G06F12/0835 , G06F12/0808 , G06F2212/1024 , G06F2212/621
摘要： Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

3. 发明申请

US20160048469A1 ARBITRATION AND HAZARD DETECTION FOR A DATA PROCESSING APPARATUS 审中-公开
标题翻译：数据处理设备的仲裁和危害检测
公开(公告)号：US20160048469A1
公开(公告)日：2016-02-18
申请号：US14801990
申请日：2015-07-17
申请人： ARM LIMITED
发明人： Alex James WAUGH
IPC分类号： G06F13/364 , G06F13/40 , G06F13/42
CPC分类号： G06F13/364 , G06F13/4031 , G06F13/4282
摘要： A device for selecting requests to be serviced in a data processing apparatus has an arbitration stage for selecting an arbitrated request from a plurality of candidate requests and a hazard detection stage for performing hazard detection to predict whether the arbitrated request selected by the arbitration stage meets a hazard condition. If the arbitrated request meets the hazard condition, the hazard detection stage returns the arbitration request to the arbitration stage for a later arbitration and sets a hazard indication for the returned request. Also, the hazard detection stage controls at least one other arbitration request to be returned if it conflicts with a candidate request having the hazard indication set. This approach prevents denial of service to requests that were hazarded.
摘要翻译：一种用于在数据处理装置中选择要服务的请求的装置具有用于从多个候选请求中选择仲裁请求的仲裁阶段和用于执行危险检测的危险检测阶段，以预测仲裁阶段选择的仲裁请求是否满足危险状况。如果仲裁请求符合危险条件，则危险检测阶段将仲裁请求返回仲裁阶段进行后续仲裁，并为返回的请求设置危险指示。此外，如果危险检测阶段与具有危险指示集合的候选请求冲突，则控制至少一个另外的仲裁请求。这种方法可以防止对被危害的请求的拒绝服务。

4. 发明公开

US20230396550A1 BANDWIDTH ALLOCATION FOR NODES COUPLED TO AN INTERCONNECT 审中-公开
公开(公告)号：US20230396550A1
公开(公告)日：2023-12-07
申请号：US17829888
申请日：2022-06-01
申请人： Arm Limited
发明人： Andrew John TURNER , Shobhit SINGHAL , Alex James WAUGH , Inaki Abadia OSTA
IPC分类号： H04L47/20 , H04L47/25 , H04L47/78
CPC分类号： H04L47/20 , H04L47/25 , H04L47/781
摘要： Interconnect systems and method of operating such are disclosed. A plurality of nodes coupled via a packet transport path form an interconnect and the nodes provide ingress points to the interconnect for a plurality of packet sources. A central controller holds permitted rate indications for each of the plurality of packet sources, in accordance with which each packet source sends packets via the interconnect. The nodes each respond to packet collision event at that node by sending a collision report to the central controller. In response the central controller, in respect of a collision pair of packet sources associated with the packet collision, decreases the permitted rate indication corresponding to a packet source of the collision pair of packet sources which currently has the higher permitted rate indication. Periodically the permitted rate indications of all of the packet sources are increased, subject to a maximum permitted rate indication for each.

5. 发明申请

US20210103543A1 NON-FORWARDABLE TRANSFERS 有权
公开(公告)号：US20210103543A1
公开(公告)日：2021-04-08
申请号：US16593127
申请日：2019-10-04
申请人： Arm Limited
发明人： Phanindra Kumar MANNAVA , Bruce James MATHEWSON , Klas Magnus BRUCE , Damien Guillaume Pierre PAYET , Jamshed JALAL , Alex James WAUGH
IPC分类号： G06F13/40 , G06F13/16 , G06F12/0815
摘要： An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

6. 发明申请

US20210103493A1 MEMORY INTERFACE HAVING DATA SIGNAL PATH AND TAG SIGNAL PATH 有权
公开(公告)号：US20210103493A1
公开(公告)日：2021-04-08
申请号：US16594223
申请日：2019-10-07
申请人： Arm Limited
发明人： Bruce James MATHEWSON , Phanindra Kumar MANNAVA , Michael Andrew CAMPBELL , Alexander Alfred HORNUNG , Alex James WAUGH , Klas Magnus BRUCE , Richard Roy GRISENTHWAITE
IPC分类号： G06F11/10 , G06F11/30 , G11C29/18
摘要： A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

7. 发明申请

US20210026554A1 METHODS AND APPARATUS FOR SERVICING DATA ACCESS REQUESTS 有权
公开(公告)号：US20210026554A1
公开(公告)日：2021-01-28
申请号：US16521723
申请日：2019-07-25
申请人： Arm Limited
发明人： Andrew John TURNER , Alex James WAUGH , Geoffray LACOURBA , Fergus Wilson MACGARRY
IPC分类号： G06F3/06
摘要： An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

8. 发明申请

US20200374377A1 HANDLING RESETS IN A SYSTEM WITH MULTIPLE RESET DOMAINS 审中-公开
公开(公告)号：US20200374377A1
公开(公告)日：2020-11-26
申请号：US16417925
申请日：2019-05-21
申请人： Arm Limited
发明人： João Carlos Mateus da Silva MARTINS , Alex James WAUGH
IPC分类号： H04L29/14 , H04L12/823 , H04L12/841 , H04L29/06 , H04L12/715
摘要： An apparatus for handling resets corresponding to multiple reset domains comprises a transport network interconnecting elements to enable data to be transferred from one element to another, ingress circuitry to couple elements to the transport network, and egress circuitry to couple the transport network to the elements. The ingress circuitry couples source elements to the transport network, and is responsive to receiving data from a source element to generate at least one transport packet in order to send that data over the transport network. Each transport packet comprises a reset domain indicator indicative of the reset domain in which the source element operates. The egress circuitry couples the transport network to destination elements and, whilst a reset of a particular reset domain is asserted, discards transport packets for which the reset domain indicator indicates the particular reset domain.

9. 发明申请

US20200341536A1 APPARATUS AND METHOD FOR MANAGING A CACHE 审中-公开
公开(公告)号：US20200341536A1
公开(公告)日：2020-10-29
申请号：US16397025
申请日：2019-04-29
申请人： Arm Limited
发明人： Alex James WAUGH
IPC分类号： G06F1/3287 , G06F12/0895 , G06F1/28 , G06F1/3234
摘要： An apparatus and method are provided for managing a cache. The cache is arranged to comprise a plurality of cache sections, where each cache section is powered independently of the other cache sections in the plurality of cache sections, and the apparatus has power control circuitry to control power to each of the cache sections. The power control circuitry is responsive to a trigger condition indicative of an ability to operate the cache in a power saving mode, to perform a latency evaluation process to determine a latency indication for each of the cache sections, and to control which of a subset of the cache sections to power off in dependence on the latency indication. This can allow the power consumption savings realised by turning off one or more cache sections to be optimised to take into account the current system state.

10. 发明申请

US20170091113A1 TRANSLATIONS BETWEEN VIRTUAL AND PHYSICAL ADDRESSES 审中-公开
公开(公告)号：US20170091113A1
公开(公告)日：2017-03-30
申请号：US14867454
申请日：2015-09-28
申请人： ARM LIMITED
发明人： Alex James WAUGH
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F11/073 , G06F11/0793 , G06F12/1027 , G06F2212/1032 , G06F2212/68
摘要： There is provided a data processing apparatus comprising: processing circuitry to speculatively execute an instruction referencing a virtual address. Lookup circuitry receives the virtual address from the processing circuitry. The lookup circuitry comprises storage circuitry to store at least one virtual address and page walking circuitry to perform a page walk on further storage circuitry, in dependence on the virtual address being unlisted by the storage circuitry, to determine whether a correspondence between a physical address and the virtual address exists. The lookup circuitry signals an error when the correspondence cannot be found and, in response to the error being signaled, the storage circuitry stores an entry comprising the virtual address.

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