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1. 发明申请

US20070285115A1 UNIVERSAL WAFER CARRIER FOR WAFER LEVEL DIE BURN-IN 失效
标题翻译：通用水平滚轮加速器
公开(公告)号：US20070285115A1
公开(公告)日：2007-12-13
申请号：US11841566
申请日：2007-08-20
申请人： Alan Wood , Tim Corbett , Warren Farnworth
发明人： Alan Wood , Tim Corbett , Warren Farnworth
IPC分类号： G01R31/02 , G01R1/06
CPC分类号： G01R31/2863
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
摘要翻译：用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。刚性基板在其上具有与晶片电接触的导体。在老化和电气测试完成之前，测试夹具不需要打开。在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

2. 发明申请

US20050237075A1 Method for testing using a universal wafer carrier for wafer level die burn-in 失效
公开(公告)号：US20050237075A1
公开(公告)日：2005-10-27
申请号：US11170852
申请日：2005-06-30
申请人： Alan Wood , Tim Corbett
发明人： Alan Wood , Tim Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/26 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/13 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： H01L24/80 , G01R1/0466 , G01R1/0483 , G01R1/0491 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2855 , G01R31/2863 , G01R31/2867 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/20 , H01L22/22 , H01L23/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

3. 发明申请

US20070103180A1 Universal wafer carrier for wafer level die burn-in 审中-公开
公开(公告)号：US20070103180A1
公开(公告)日：2007-05-10
申请号：US11588707
申请日：2006-10-27
申请人： Alan Wood , Tim Corbett
发明人： Alan Wood , Tim Corbett
IPC分类号： G01R31/02
CPC分类号： H01L24/80 , G01R1/0466 , G01R1/0483 , G01R1/0491 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2855 , G01R31/2863 , G01R31/2867 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/20 , H01L22/22 , H01L23/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

4. 发明申请

US20050237077A1 Method for testing using a universal wafer carrier for wafer level die burn-in 有权
标题翻译：用于晶圆级模具老化的通用晶片载体的测试方法
公开(公告)号：US20050237077A1
公开(公告)日：2005-10-27
申请号：US11171153
申请日：2005-06-30
申请人： Alan Wood , Tim Corbett
发明人： Alan Wood , Tim Corbett
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/26 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/13 , H05K3/00 , H05K3/40 , H05K3/42
CPC分类号： H01L24/80 , G01R1/0466 , G01R1/0483 , G01R1/0491 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2855 , G01R31/2863 , G01R31/2867 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/20 , H01L22/22 , H01L23/13 , H01L2224/16145 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1433 , H01L2924/15151 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723
摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
摘要翻译：一个可重复使用的老化/测试夹具，用于测试由半个半部组成的半导体晶圆上的无引脚骰子。测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。刚性基板在其上具有与晶片电接触的导体。在老化和电气测试完成之前，测试夹具不需要打开。在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

5. 发明申请

US20070170350A1 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
公开(公告)号：US20070170350A1
公开(公告)日：2007-07-26
申请号：US11727545
申请日：2007-03-27
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
IPC分类号： H01L27/00
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

6. 发明申请

US20060243889A1 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
公开(公告)号：US20060243889A1
公开(公告)日：2006-11-02
申请号：US11476015
申请日：2006-06-28
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Alan Wood , Peter Benson , James Wark , David Hembree , Kyle Kirby , Charles Watkins , Salman Akram
IPC分类号： H01L27/00
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

7. 发明申请

US20060234422A1 Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers 有权
标题翻译：用于封装的微电子成像器的间隔器以及制造和使用间隔件用于成像器的晶片级封装的方法
公开(公告)号：US20060234422A1
公开(公告)日：2006-10-19
申请号：US11451398
申请日：2006-06-13
申请人： Warren Farnworth , Alan Wood , James Wark , David Hembree , Rickie Lake
发明人： Warren Farnworth , Alan Wood , James Wark , David Hembree , Rickie Lake
IPC分类号： H01L21/00
CPC分类号： H01L31/0203 , H01L27/14618 , H01L27/14625 , H01L27/14634 , H01L27/14683 , H01L2224/48227 , H01L2224/48091 , H01L2924/00014
摘要： Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web. As such, the web does not outgas contaminants into the compartments in which the image sensors are housed.
摘要翻译：包装微电子成像仪和封装的微电子成像仪的方法。这种方法的实施例可以包括提供具有以模片图案布置的多个成像模具的成像工件，并提供覆盖基板，期望的辐射可以通过该基板传播。成像器裸片包括耦合到图像传感器的图像传感器和集成电路。该方法还包括提供具有包括粘合剂并具有布置成与图像传感器对准的开口的腹板的间隔件。例如，网可以是具有粘合剂涂层的膜，或者网本身可以是一层粘合剂。该方法通过将成像器工件与盖基板组装成使得（a）间隔件位于成像器工件和盖基板之间，并且（b）开口与图像传感器对准，该方法继续。在成像器工件和盖基板都已经粘附在卷材上之后，连接的卷材不固化。因此，纸幅不会将污染物排出到其中容纳图像传感器的隔室中。

8. 发明申请

US20060220665A1 Alignment fences and devices and assemblies including the same 审中-公开
标题翻译：对齐栅栏和包括它们的装置和组件
公开(公告)号：US20060220665A1
公开(公告)日：2006-10-05
申请号：US11445684
申请日：2006-06-01
申请人： Salman Akram , Alan Wood , Warren Farnworth
发明人： Salman Akram , Alan Wood , Warren Farnworth
IPC分类号： G01R31/02
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A fence is configured to receive and align a semiconductor device, such as a flip-chip type semiconductor device, with a substrate. The fence may include a plurality of adjacent, mutually adhered regions, which may comprise layers. One or more laterally recessed regions may be located at one or more corners of a receptacle formed by the fence to facilitate rough alignment of a semiconductor device with the substrate. The receptacle of the fence may include edges that are configured to progressively align a semiconductor device with the substrate.
摘要翻译：栅栏被配置为接收和对齐诸如倒装芯片型半导体器件的半导体器件与衬底。栅栏可以包括多个相邻的相互粘合的区域，其可以包括层。一个或多个横向凹陷区域可以位于由栅栏形成的容器的一个或多个拐角处，以便半导体器件与衬底的粗略对准。栅栏的插座可以包括被配置为使半导体器件与衬底逐渐对准的边缘。

9. 发明申请

US20060197235A1 Electronic device components including protective layers on surfaces thereof 审中-公开
标题翻译：电子器件部件包括其表面上的保护层
公开(公告)号：US20060197235A1
公开(公告)日：2006-09-07
申请号：US11413414
申请日：2006-04-27
申请人： Warren Farnworth , Alan Wood
发明人： Warren Farnworth , Alan Wood
IPC分类号： H01L23/28
CPC分类号： H01L21/44 , B33Y10/00 , B33Y30/00 , B33Y40/00 , B33Y80/00 , H01L23/3157 , H01L23/3192 , H01L2924/00013 , H01L2924/0002 , H01L2224/29099 , H01L2924/00
摘要： An electronic device component, such as a semiconductor element device or semiconductor device component includes on selected portions of a surface thereof. One or more conductive features may be exposed through the protective element. The protective element includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually adhered regions may comprise the same material. They may be substantially free of voids or air pockets. The electronic device may be an individual component or it may be physically secured to one or more other components, such as devices that have yet to be singulated from a large-scale substrate, such as a full or partial wafer or a strip or array of carriers.
摘要翻译：诸如半导体元件器件或半导体器件部件的电子器件部件包括在其表面的选定部分上。可以通过保护元件暴露一个或多个导电特征。保护元件包括多个相邻的相互粘合的区域。相邻的相互粘合的区域可以包括相同的材料。它们可以基本上没有空隙或气穴。电子设备可以是单个组件，或者它可以物理地固定到一个或多个其他组件，诸如尚未从大规模衬底（例如，全部或部分晶片）或者一个或多个承运人

10. 发明申请

US20060035415A1 Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages 有权
标题翻译：用于制造图像传感器封装等的框架结构和半导体附着工艺以及所产生的封装
公开(公告)号：US20060035415A1
公开(公告)日：2006-02-16
申请号：US10919604
申请日：2004-08-16
申请人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
发明人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
IPC分类号： H01L21/50
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used for the packages.
摘要翻译：诸如图像传感器封装的半导体封装以及制造方法。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。各种外部连接方法可用于包装。

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