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1. 发明申请

US20090210566A1 MULTI-CHIP DIGITAL SYSTEM SIGNAL IDENTIFICATION APPARATUS 失效
标题翻译：多芯片数字系统信号识别装置
公开(公告)号：US20090210566A1
公开(公告)日：2009-08-20
申请号：US12032990
申请日：2008-02-18
申请人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
发明人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
IPC分类号： G06F3/00
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译：本发明提供一种系统。该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号通过输出引脚基于自识别控制信号。每个输出引脚耦合到外部系统。处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。

2. 发明授权

US07716546B2 System and method for improved LBIST power and run time 有权
标题翻译：改善LBIST功率和运行时间的系统和方法
公开(公告)号：US07716546B2
公开(公告)日：2010-05-11
申请号：US11866787
申请日：2007-10-03
申请人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
发明人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译：一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。

3. 发明申请

US20090094496A1 System and Method for Improved LBIST Power and Run Time 有权
标题翻译：改进LBIST功率和运行时间的系统和方法
公开(公告)号：US20090094496A1
公开(公告)日：2009-04-09
申请号：US11866787
申请日：2007-10-03
申请人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
发明人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
IPC分类号： G06F11/25
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译：一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。

4. 发明授权

US07266463B2 Signal identification method and apparatus for analogue electrical systems 失效
标题翻译：模拟电气系统的信号识别方法和装置
公开(公告)号：US07266463B2
公开(公告)日：2007-09-04
申请号：US11126120
申请日：2005-05-10
申请人： Robert Christopher Dixon , John Wayne Hartfiel , Hein Minh Le , Tung Nguyen Pham
发明人： Robert Christopher Dixon , John Wayne Hartfiel , Hein Minh Le , Tung Nguyen Pham
IPC分类号： G01R19/00
CPC分类号： G01R31/3167 , G01R31/31924
摘要： An apparatus, a method, and a computer program product are provided for identifying signals in analogue electrical systems. The ID select signals that control the timing of this signal identification circuit comprise sequential numbers that count up and identify a corresponding signal. The signals to be identified are located on a group of input/output (I/O) pins. One multiplexer (first) selects a specific I/O pin in response to the ID select signals. An isolated voltage source is connected to this multiplexer and provides the selected signal to another multiplexer (second). The second multiplexer switches from this isolated voltage source to ground potential in response to the ID select signals. The isolated voltage source floats at the DC level of the selected I/O driver pin. Therefore, by connecting to the selected signal's I/O pin and the output of the second multiplexer, the selected signal can be identified and then probed.
摘要翻译：提供了用于识别模拟电气系统中的信号的装置，方法和计算机程序产品。控制该信号识别电路的定时的ID选择信号包括向上计数并识别相应信号的顺序号码。要识别的信号位于一组输入/输出（I / O）引脚上。一个多路复用器（第一）响应于ID选择信号选择一个特定的I / O引脚。隔离电压源连接到该多路复用器，并将所选择的信号提供给另一个多路复用器（第二）。响应于ID选择信号，第二多路复用器从该隔离电压源切换到接地电位。隔离电压源浮动在所选I / O驱动器引脚的直流电平上。因此，通过连接到所选信号的I / O引脚和第二多路复用器的输出，可以识别所选择的信号，然后探测。

5. 发明授权

US08020058B2 Multi-chip digital system having a plurality of controllers with self-identifying signal 失效
标题翻译：具有多个具有自识别信号的控制器的多芯片数字系统
公开(公告)号：US08020058B2
公开(公告)日：2011-09-13
申请号：US12032990
申请日：2008-02-18
申请人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
发明人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
IPC分类号： G01R31/28
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译：本发明提供一种系统。该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号通过输出引脚基于自识别控制信号。每个输出引脚耦合到外部系统。处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。

6. 发明授权

US07409469B2 Multi-chip digital system having a plurality of controllers with input and output pins wherein self-identification signal are received and transmitted 失效
标题翻译：具有多个具有输入和输出引脚的控制器的多芯片数字系统，其中接收和发送自识别信号
公开(公告)号：US07409469B2
公开(公告)日：2008-08-05
申请号：US10870459
申请日：2004-06-17
申请人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
发明人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
IPC分类号： G06F13/00 , G06F1/26 , G06F15/02 , G01R31/38
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system, comprising a controller and a processor. The controller comprises at least an output pin and a plurality of input pins, and is configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. The processor is coupled to the controller and configured to generate self-identify control signals and to transmit the self-identify control signals to the controller.
摘要翻译：本发明提供一种包括控制器和处理器的系统。所述控制器至少包括输出引脚和多个输入引脚，并且被配置为通过所述多个输入引脚中的一个或多个接收自识别控制信号，并且基于所述输出引脚基于所述输出引脚传输控制器自识别信号自我识别控制信号。处理器耦合到控制器并被配置为产生自识别控制信号并将自识别控制信号发送到控制器。

7. 发明授权

US06931561B2 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components 失效
标题翻译：使用多个存储和多路复用器组件异步地连接高速时钟域和低速时钟域的装置和方法
公开(公告)号：US06931561B2
公开(公告)日：2005-08-16
申请号：US09978357
申请日：2001-10-16
申请人： Gary Dale Carpenter , Tung Nguyen Pham
发明人： Gary Dale Carpenter , Tung Nguyen Pham
IPC分类号： G06F5/06 , H04L7/02 , G06F1/12 , H04L7/00
CPC分类号： G06F5/06 , H04L7/02
摘要： Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one half being synchronized to a first clock and the second half being synchronized to a second clock. The first half and the second half are mirror images of each other. Each half has at least one storage component, such as a register and a flip-flop, for storing a valid bit as well as data, and at least one multiplexer component for gating the storage component. The valid bit is used to control the multiplexer at a receiving half. When transferring from a high-speed clock domain to a low-speed clock domain, the high-speed clock domain may probe the received data and/or the valid bit stored in the low-speed clock domain before the high-speed clock domain sends additional data.
摘要翻译：提供了在高速时钟域和低速时钟域之间异步传输数据的接口电路。接口电路被分成两半，其中一半与第一时钟同步，而后半部分与第二时钟同步。上半场和下半场是彼此的镜像。每一半具有用于存储有效位和数据的至少一个存储组件，例如寄存器和触发器，以及用于门控存储组件的至少一个多路复用器组件。有效位用于在接收端控制多路复用器。当从高速时钟域传输到低速时钟域时，高速时钟域可以在高速时钟域发送之前探测存储在低速时钟域中的接收数据和/或有效位附加数据。

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