专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08896670B2 Image processing device, image processing method, and program 有权
标题翻译：图像处理装置，图像处理方法和程序
公开(公告)号：US08896670B2
公开(公告)日：2014-11-25
申请号：US13252473
申请日：2011-10-04
申请人： Tadashi Yamaguchi
发明人： Tadashi Yamaguchi
IPC分类号： H04N13/02 , H04N13/00
CPC分类号： H04N13/239 , H04N13/189 , H04N13/289
摘要： An image processing device includes a distance data analysis unit that analyzes subject distance information with the partial region units of captured images having different viewpoints, and a data generation unit that determines whether a recorded image or an output image is set to a two-dimensional image or set to a three-dimensional image depending on the analysis result, and generates the recorded or output image based on the determination result, wherein the data generation unit determines a recall level of stereoscopic vision in three-dimensional display based on the analysis result, and if it is determined that the recall level of stereoscopic vision is low, generates a two-dimensional image as the recorded or output image, and if it is determined that the recall level of stereoscopic vision is high, generates a three-dimensional image as the recorded or output image.
摘要翻译：一种图像处理装置，包括距离数据分析单元，其利用具有不同视点的拍摄图像的部分区域单位来分析被摄体距离信息;以及数据生成单元，确定记录图像或输出图像是否被设置为二维图像或者根据分析结果设置为三维图像，并且基于确定结果生成记录或输出图像，其中数据生成单元基于分析结果确定三维显示中的立体视觉的回忆水平，并且如果确定立体视觉的回放水平低，则生成作为记录或输出图像的二维图像，并且如果确定立体视觉的回忆水平高，则生成三维图像为记录或输出图像。

2. 发明授权

US08593531B2 Imaging device, image processing method, and computer program 有权
标题翻译：成像设备，图像处理方法和计算机程序
公开(公告)号：US08593531B2
公开(公告)日：2013-11-26
申请号：US13267112
申请日：2011-10-06
申请人： Tadashi Yamaguchi
发明人： Tadashi Yamaguchi
IPC分类号： H04N5/228 , H04N5/232 , G06K9/40 , G02F1/01 , G02B21/00
CPC分类号： H04N5/23212 , H04N5/2258 , H04N5/23287 , H04N5/3696
摘要： An imaging device includes: a first imaging unit which does not include a phase difference detecting pixel on an imaging element; a second imaging unit which includes a phase difference detecting pixel on an imaging element; a pixel comparing unit which compares first obtained image obtained by the first imaging unit with a second obtained image obtained by the second imaging unit; a correcting unit which corrects phase difference information obtained by the second imaging unit based on a comparison result by the image comparing unit; a phase difference applying unit which applies the phase difference information corrected by the correcting unit to the first obtained image; and a recording unit which records image information.
摘要翻译：一种成像装置包括：第一成像单元，其不包括成像元件上的相位差检测像素; 第二成像单元，其包括成像元件上的相位差检测像素; 像素比较单元，其将由第一成像单元获得的第一获得图像与由第二成像单元获得的第二获得图像进行比较; 校正单元，其基于图像比较单元的比较结果校正由第二成像单元获得的相位差信息; 相位差施加单元，将由校正单元校正的相位差信息应用于第一获得图像; 以及记录图像信息的记录单元。

3. 发明授权

US08338247B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08338247B2
公开(公告)日：2012-12-25
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译：提高半导体器件的性能。在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

4. 发明申请

US20120098930A1 IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM 审中-公开
标题翻译：图像处理设备，图像处理方法和程序
公开(公告)号：US20120098930A1
公开(公告)日：2012-04-26
申请号：US13235835
申请日：2011-09-19
申请人： Tadashi YAMAGUCHI
发明人： Tadashi YAMAGUCHI
IPC分类号： H04N13/00
CPC分类号： H04N13/139 , H04N13/161
摘要： An image processing device including a video signal output section which executes resolution conversion of an image, where in a case where a plurality of different images are included in an input image which is the resolution conversion target, the video signal output section executes a reference pixel setting process, which is the same as a reference pixel setting process of an image edge portion, at the time of a pixel value calculation of an output image in the vicinity of the image boundary, and a pixel value of an output pixel in the vicinity of the image boundary is determined using a pixel value of a reference pixel set using the image edge process.
摘要翻译：一种图像处理装置，包括执行图像的分辨率转换的视频信号输出部分，其中在多个不同图像被包括在作为分辨率转换目标的输入图像中的情况下，视频信号输出部分执行参考像素在图像边界附近的输出图像的像素值计算时和图像边缘部分的参考像素设置处理相同的设置处理以及附近的输出像素的像素值使用使用图像边缘处理的参考像素的像素值来确定图像边界。

5. 发明申请

US20120097977A1 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US20120097977A1
公开(公告)日：2012-04-26
申请号：US13253482
申请日：2011-10-05
申请人： Tadashi YAMAGUCHI
发明人： Tadashi YAMAGUCHI
IPC分类号： H01L29/772 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26566 , H01L21/30608 , H01L21/3065 , H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.
摘要翻译：本发明的半导体器件具有形成在pMIS区域中的（110）面取向硅衬底和p沟道型场效应晶体管。 p沟道型场效应晶体管包括通过栅极绝缘膜设置的栅电极和设置在栅极电极的相对侧上的设置在硅衬底中的沟槽内的源极/漏极区域，并且包括晶格常数大于Si的SiGe 。沟槽具有（100）平面取向的第一倾斜表面和在位于栅电极侧的侧壁部分处与第一倾斜表面交叉的（100）平面取向的第二倾斜表面。通过该结构，在基板的表面（110）面和（100）面之间形成的角度为45°，使得第一倾斜面形成为相对锐角。这可以有效地将压应变应用于p沟道型MISFET的沟道区。

6. 发明授权

US08084343B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08084343B2
公开(公告)日：2011-12-27
申请号：US12977573
申请日：2010-12-23
申请人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
发明人： Tadashi Yamaguchi , Koyu Asai , Mahito Sawada , Kiyoteru Kobayashi , Tatsunori Murata , Satoshi Shimizu
IPC分类号： H01L21/20
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76837 , H01L23/53295 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film.
摘要翻译：为了阻止通过HDP-CVD等形成层间绝缘膜时产生的氢离子，从而抑制氢离子对器件的不利影响，在包括接触层，金属互连和层间绝缘的半导体器件中在其上形成有栅电极的半导体衬底上，通过使用含氢原子的气体的偏压施加等离子体CVD在金属互连上形成层间绝缘膜，并且在金属互连的底层设置氮氧化硅膜，层间绝缘膜。

7. 发明申请

US20110237061A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20110237061A1
公开(公告)日：2011-09-29
申请号：US13046761
申请日：2011-03-13
申请人： Tadashi Yamaguchi , Takuya Futase
发明人： Tadashi Yamaguchi , Takuya Futase
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/67207 , H01L21/67748 , H01L21/68735 , H01L21/68764 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.
摘要翻译：本发明改进了通过自对准硅化物工艺形成金属硅化物层的半导体器件的性能。通过部分反应型的自对准硅化物工艺，在不使用整个反应类型的自对准硅化物工艺的情况下，在第一和第二栅电极，n +型半导体区域和p +型半导体区域的表面上形成金属硅化物层。在用于形成金属硅化物层的热处理中，通过不使用灯或激光器的退火设备对半导体晶片进行热处理，但是使用具有碳加热器的导热退火装置，以小的热预算形成薄金属硅化物层并且通过第一热处理在金属硅化物层中形成高精度的NiSi微晶。

8. 发明授权

US08022445B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08022445B2
公开(公告)日：2011-09-20
申请号：US12510026
申请日：2009-07-27
申请人： Tadashi Yamaguchi , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
发明人： Tadashi Yamaguchi , Keiichiro Kashihara , Tomonori Okudaira , Toshiaki Tsutsumi
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7848
摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。

9. 发明授权

US07936016B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07936016B2
公开(公告)日：2011-05-03
申请号：US12413980
申请日：2009-03-30
申请人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
发明人： Toshiaki Tsutsumi , Tomonori Okudaira , Keiichiro Kashihara , Tadashi Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译：提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一层间绝缘膜依次层叠在金属硅化物上。在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

10. 发明申请

US20100230761A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100230761A1
公开(公告)日：2010-09-16
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译：提高半导体器件的性能。在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式