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1. 发明授权

US06438061B1 Dynamic random access memory with low power consumption 有权
公开(公告)号：US06438061B1
公开(公告)日：2002-08-20
申请号：US09907449
申请日：2001-07-18
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： There provides a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside and without causing occurrence of malfunction at times of low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to a power supply control signal CONT inputted from outside, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.

2. 发明授权

US06574150B2 Dynamic random access memory with low power consumption 有权
标题翻译：具有低功耗的动态随机存取存储器
公开(公告)号：US06574150B2
公开(公告)日：2003-06-03
申请号：US10175859
申请日：2002-06-21
申请人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
发明人： Junichi Suyama , Wataru Nagai , Akihiro Hirota , Shota Ohtsubo
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/147
摘要： A low power consumption type dynamic random access memory (DRAM) operable with reduced current consumption responsive to an external signal, without causing occurrence of malfunction during low current consumption. An input circuit for receiving signals, a memory array for holding data, and a peripheral circuit for controlling the memory array are driven by an internal voltage supplied by two groups of internal voltage receiving circuits, while an output circuit for outputting signals is driven by an external power supply. The two groups of internal voltage receiving circuits are deactivated in response to an externally provided power supply control signal, and the output circuit is controlled so as to be in a high impedance condition with voltage of the external power supply being applied thereto.
摘要翻译：低功耗型动态随机存取存储器（DRAM），可以响应于外部信号而以可减小的电流消耗进行操作，而不会在低电流消耗期间发生故障。用于接收信号的输入电路，用于保持数据的存储器阵列和用于控制存储器阵列的外围电路由内部电压接收电路组提供的内部电压驱动，而用于输出信号的输出电路由外部电源。两组内部电压接收电路响应于外部提供的电源控制信号被去激活，并且输出电路被控制成在施加外部电源的电压的情况下处于高阻抗状态。

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