专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08310478B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08310478B2
公开(公告)日：2012-11-13
申请号：US11477741
申请日：2006-06-30
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
IPC分类号： G06F3/038
CPC分类号： H01L27/0207 , G09G3/3688 , H01L27/105 , H01L27/11 , H01L27/1116
摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.
摘要翻译：集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND，以及与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端处的焊盘PD。焊盘PD设置在第一和第二晶体管NTr1和PTr1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr1和PTr1中的至少一个晶体管的一部分或全部重叠。

2. 发明授权

US08188544B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08188544B2
公开(公告)日：2012-05-29
申请号：US11477720
申请日：2006-06-30
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
IPC分类号： H01L23/62
CPC分类号： G09G3/3688 , G02F1/13452 , G02F2202/28 , G09G3/3696 , G09G2300/0426 , G09G2310/027
摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.
摘要翻译：集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠部分或全部静电放电保护元件ESDx。

3. 发明申请

US20110128274A1 Integrated Circuit Device and Electronic Instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20110128274A1
公开(公告)日：2011-06-02
申请号：US13022995
申请日：2011-02-08
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru ITO , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru ITO , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Takayuki Saiki , Hiroyuki Takamiya
IPC分类号： G06F3/038
CPC分类号： H01L27/0207 , G09G3/3688 , H01L27/105 , H01L27/11 , H01L27/1116
摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.
摘要翻译：集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND，以及与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端处的焊盘PD。焊盘PD设置在第一和第二晶体管NTr1和PTr1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr1和PTr1中的至少一个晶体管的一部分或全部重叠。

4. 发明授权

US07755587B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07755587B2
公开(公告)日：2010-07-13
申请号：US11477715
申请日：2006-06-30
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/2096 , G09G3/3648 , G09G3/3677 , G09G3/3696 , G09G2300/0426 , G09G2310/027 , G09G2310/0278 , G09G2310/0289 , G09G2320/0285 , G09G2320/0673 , G09G2330/028 , G09G2330/04 , G09G2360/18
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.
摘要翻译：集成电路装置包括：当从集成电路装置的短边的第一侧向与第一侧相反的第三侧的方向为方向D1时，沿着方向D1设置的第一至第N电路块CB1至CBN为方向D1，从集成电路装置的长边的第二侧向与第二侧相反的第四侧的方向为方向D2。电路块CB1至CBN的两端的至少一个电路块是用于驱动扫描线的扫描驱动器块。或者，扫描驱动块SB沿方向D2的第一至第N电路块侧的方向D1设置。

5. 发明授权

US07590015B2 Integrated circuit device and electronic instrument 失效
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07590015B2
公开(公告)日：2009-09-15
申请号：US11889286
申请日：2007-08-10
申请人： Satoru Kodaira , Hiroshi Kiya
发明人： Satoru Kodaira , Hiroshi Kiya
IPC分类号： G11C7/00
CPC分类号： G11C29/816 , G11C29/806 , G11C29/81 , G11C2029/0401
摘要： An integrated circuit device includes a data driver block, a memory block, an information storage block in which an address of a defective cell of the memory block is programmed and stored as a defective address, and a switch control circuit which performs control for switching access to the defective cell to access to a redundant cell. A row address of the defective cell having the row address and a column address is stored in the information storage block as the defective address. The switch control circuit performs control for switching access to the defective cell to access to the redundant cell by comparing a row address for display panel access with the defective address during the display panel access and comparing a row address for host access using the row address and a column address with the defective address during the host access.
摘要翻译：一种集成电路装置，包括数据驱动器块，存储器块，存储块的缺陷单元的地址被编程并存储为缺陷地址的信息存储块;以及执行用于切换存取的控制的开关控制电路到有缺陷的单元以访问冗余单元。具有行地址和列地址的缺陷单元的行地址作为缺陷地址存储在信息存储块中。开关控制电路通过在显示面板访问期间比较用于显示面板访问的行地址和缺陷地址来进行对存储于冗余单元的访问的控制，并且使用行地址比较用于主机访问的行地址，以及在主机访问期间具有缺陷地址的列地址。

6. 发明授权

US07471573B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07471573B2
公开(公告)日：2008-12-30
申请号：US11270549
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G11C7/00
CPC分类号： G09G3/3685 , G09G3/20 , G09G3/3611 , G09G5/39 , G09G5/395 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0278 , G09G2360/12
摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
摘要翻译：一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

7. 发明授权

US07411804B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07411804B2
公开(公告)日：2008-08-12
申请号：US11270779
申请日：2005-11-10
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G09G3/3688 , G09G2300/0426 , G09G2310/027
摘要： An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines; and the memory block MB includes a memory cell array, a row address decoder RD, and a sense amplifier block SAB. The row address decoder RD is disposed so that a longitudinal direction of the row address decoder RD coincides with the direction D1, and the sense amplifier block SAB is disposed so that a longitudinal direction of the sense amplifier block SAB coincides with the direction D2.
摘要翻译：一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D1是从集成电路装置的第一侧向与第三方向相反的第三侧的方向时第一侧，第一侧为短边，当第二方向D 2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。电路块CB 1至CBN包括存储图像数据的至少一个存储器块MB和驱动数据线的至少一个数据驱动器块DB; 并且存储块MB包括存储单元阵列，行地址解码器RD和读出放大器块SAB。行地址解码器RD被布置成使得行地址解码器RD的纵向与方向D1一致，并且读出放大器块SAB被布置成使得读出放大器块SAB的纵向方向与方向D 2重合。

8. 发明授权

US07388803B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07388803B2
公开(公告)日：2008-06-17
申请号：US11270547
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G11C8/00 , G09G5/00
CPC分类号： G09G3/20 , G09G3/3611 , G09G2300/0426 , G09G2310/027 , G09G2310/0278 , G09G2310/08
摘要： An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.
摘要翻译：集成电路装置包括：包括多个字线的RAM块，多个位线，多个存储单元和字线控制电路; 以及基于从RAM块提供的数据驱动显示面板的多个数据线组的数据线驱动器块。数据线驱动器块包括第一至第N（N是大于1的整数）分割数据线驱动器块，驱动数据线组的不同数据线组的第一至第N分割数据线驱动器块中的每一个。字线控制电路在显示面板的一个水平扫描周期中从字线中驱动相同的字线N次。第一至第N分割数据线驱动器沿着位线延伸的第一方向布置。

9. 发明授权

US07285817B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07285817B2
公开(公告)日：2007-10-23
申请号：US11223679
申请日：2005-09-09
申请人： Kimihiro Maemura , Hitoshi Kobayashi , Tadatoshi Nakajima , Satoru Kodaira
发明人： Kimihiro Maemura , Hitoshi Kobayashi , Tadatoshi Nakajima , Satoru Kodaira
IPC分类号： H01L29/788
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a shading target region; a semiconductor element provided on the semiconductor layer in the shading target region; a first interlayer dielectric provided on the semiconductor element; a plurality of first shading layers provided on the first interlayer dielectric; a second interlayer dielectric provided on at least the first shading layers; and a second shading layer provided on the second interlayer dielectric and having a predetermined pattern. The second shading layer has such a pattern that the second shading layer is positioned at least between the adjacent first shading layers.
摘要翻译：半导体器件包括：具有阴影目标区域的半导体层; 设置在阴影对象区域的半导体层上的半导体元件; 设置在所述半导体元件上的第一层间电介质; 设置在所述第一层间电介质上的多个第一遮光层; 至少设置在第一遮光层上的第二层间电介质; 以及设置在第二层间电介质上并具有预定图案的第二遮光层。第二遮光层具有使第二遮光层至少位于相邻的第一遮光层之间的图案。

10. 发明申请

US20070013706A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013706A1
公开(公告)日：2007-01-18
申请号：US11477647
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G09G5/36 , G06F12/02
CPC分类号： G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0275 , G09G2360/12
摘要： Each of RAM blocks provided in a display memory and disposed along a first direction in which bitlines extend includes a sense amplifier circuit which outputs M-bit data upon one wordline selection (M is an integer larger than 1). At least M memory cells are arranged in each of the RAM blocks along a second direction in which wordlines extend. M sense amplifier cells to which M-bit data read from the M memory cells is input are provided in the sense amplifier circuit. L sense amplifier cells of the M sense amplifier cells are disposed at a position corresponding to L memory cells adjacent in the second direction (L is an integer which satisfies 2≦L
摘要翻译：提供在显示存储器中并沿着位线延伸的第一方向布置的每个RAM块包括读取放大器电路，其在一个字线选择（M是大于1的整数）上输出M位数据。至少M个存储单元沿着字线延伸的第二方向布置在每个RAM块中。在读出放大器电路中设置有从M个存储单元读取M位数据的M个读出放大器单元。 M个读出放大器单元的L个读出放大器单元配置在与第二方向相邻的L个存储单元对应的位置（L为满足2 <= L

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式