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1. 发明申请

US20140041551A1 PIGMENT PAINT FOR AN EXTERIOR MATERIAL HAVING GOOD WEATHER RESISTANCE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：具有良好耐候性的外部材料的颜料涂料及其制造方法
公开(公告)号：US20140041551A1
公开(公告)日：2014-02-13
申请号：US14113324
申请日：2012-03-08
申请人： Jae-Il Jeong , Nam-Il Lee , Sang-Keun Park , Jin-Hyung Lee , Kwang-Choong Kang , Byung-Ki Choi , Kwang-Soo Lim , Kil-Wan Chang
发明人： Jae-Il Jeong , Nam-Il Lee , Sang-Keun Park , Jin-Hyung Lee , Kwang-Choong Kang , Byung-Ki Choi , Kwang-Soo Lim , Kil-Wan Chang
IPC分类号： C08K3/00
CPC分类号： C08K3/0075 , B82Y30/00 , C01G7/00 , C01G7/003 , C01P2004/04 , C01P2004/64 , C01P2006/60 , C08K3/10 , C09C1/30 , C09C1/36 , C09C3/06
摘要： The present invention relates to a pigment paint for an exterior material and to a method for manufacturing the same. The pigment paint comprises: a flake matrix, a first metal oxide layer coated on the upper portion of the transparent matrix, an oxide layer containing MgO—SiO2 coated on the upper portion of the first metal oxide layer, and a second metal oxide layer coated on the upper portion of the oxide layer. In order to ensure humidity resistance and weather resistance required for a lustrous pigment paint for exterior materials, a cerium layer and an aluminum oxide layer are further coated. Properties such as high luminance, high chromaticity, and high gloss, which could not be achieved using conventional techniques, can be achieved and a pigment paint having a multi-colored pearl luster can be provided.
摘要翻译：本发明涉及一种外用材料用颜料涂料及其制造方法。颜料涂料包括：薄片基质，涂覆在透明基体的上部的第一金属氧化物层，涂覆在第一金属氧化物层的上部的含有MgO-SiO 2的氧化物层和涂覆的第二金属氧化物层在氧化物层的上部。为了确保外部材料的光泽颜料涂料所需的耐湿性和耐候性，进一步涂覆铈层和氧化铝层。可以实现使用常规技术无法实现的诸如高亮度，高色度和高光泽度的性能，并且可以提供具有多色珍珠光泽的颜料涂料。

2. 发明授权

US06377226B1 Dual band antenna 失效
标题翻译：双频天线
公开(公告)号：US06377226B1
公开(公告)日：2002-04-23
申请号：US08845959
申请日：1997-04-30
申请人： Dong-In Ha , Sang-Keun Park , Goudelev Alexandre , Krylov Konstantin
发明人： Dong-In Ha , Sang-Keun Park , Goudelev Alexandre , Krylov Konstantin
IPC分类号： H01Q920
CPC分类号： H01Q13/08 , H01Q1/242 , H01Q1/362 , H01Q5/357 , H01Q5/48 , H01Q9/20 , H01Q9/32 , H01Q11/08 , H04B1/3833
摘要： A dual band antenna for a mobile communication system which includes: a metal tube having an open end; a coaxial feed line having inner and outer conductors, with one portion of the coaxial line inserted into the metal tube, a ground plane connected to a portion of the metal tube opposite the open end and to the outer conductor of the coaxial feed line, and, a signal line electrically coupled to the inner conductor and protruding from the metal tube at the open end thereof. Preferably, the dimensions of the metal tube, the coaxial feed line and the signal line are selected such that the antenna is impedance matched to the coaxial feed line over the dual operating band, thereby obviating the need for a separate matching network.
摘要翻译：一种用于移动通信系统的双频带天线，其包括：具有开口端的金属管; 具有内部和外部导体的同轴馈电线，同轴线的一部分插入金属管中，与金属管的与开放端相对的部分和同轴馈电线的外部导体连接的接地平面，以及信号线，电耦合到内部导体并在其开口端从金属管突出。优选地，选择金属管，同轴馈电线和信号线的尺寸，使得天线在双工作频带上与同轴馈电线阻抗匹配，从而避免了对单独的匹配网络的需要。

3. 发明授权

US07139847B2 Semiconductor memory device having externally controllable data input and output mode 失效
标题翻译：具有外部可控数据输入和输出模式的半导体存储器件
公开(公告)号：US07139847B2
公开(公告)日：2006-11-21
申请号：US10900506
申请日：2004-07-27
申请人： Yong-jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
发明人： Yong-jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
IPC分类号： G06F3/00
CPC分类号： G11C7/1045 , G11C7/1078
摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.
摘要翻译：提供具有外部可控输入和输出模式的半导体存储器件。半导体存储器件包括第一和第二多个焊盘以及电连接到第一多个焊盘和第二多个焊盘的输入和输出模式设置电路，用于产生多个输入和输出模式信号。输入和输出模式设置电路切断从第一多个焊盘接收的信号，将每个输入和输出模式信号的电平控制在逻辑高电平和逻辑低电平，并设置输入和输出当在测试模式中将高于半导体存储器件的电源电压的电压施加到第二多个焊盘中的一个焊盘时，高电压不施加到第二多个焊盘，并且输入和输出模式设置电路将输入和输出模式信号的电平控制在逻辑高电平或逻辑低电平，从而将半导体存储器在正常操作期间具有响应于从所述多个焊盘接收的信号的一个输入和输出模式的装置。因此，可以从外部改变半导体存储器件的输入和输出模式。

4. 发明授权

US08193507B2 System and method for compensating for anode gain non-uniformity in multi-anode position sensitive photomultiplier tube 有权
标题翻译：用于补偿多阳极位置敏感光电倍增管中阳极增益不均匀的系统和方法
公开(公告)号：US08193507B2
公开(公告)日：2012-06-05
申请号：US12791988
申请日：2010-06-02
申请人： Jae Sung Lee , Chan Mi Lee , Sun Il Kwon , Mikiko Ito , Hyun Suk Yoon , Sang Keun Park , Seong Jong Hong , Dong Soo Lee
发明人： Jae Sung Lee , Chan Mi Lee , Sun Il Kwon , Mikiko Ito , Hyun Suk Yoon , Sang Keun Park , Seong Jong Hong , Dong Soo Lee
IPC分类号： G01T1/208
CPC分类号： G01T1/248 , G01T1/2018
摘要： The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.
摘要翻译：本发明涉及一种用于补偿多阳极位置敏感光电倍增管（PS-PMT）中的阳极增益不均匀性的系统和方法，其中补偿单元设置在多阳极位置敏感光电倍增管和位置检测电路单元，并且被配置为使输入到位置检测电路单元的电流信号均匀，从而补偿阳极增益不均匀。根据本发明，使用用于改变电阻的补偿单元。因此，可以补偿PS-PMT的每个阳极的增益不均匀性的优点。此外，通过改变补偿单元的可变电阻的电阻值来补偿PS-PMT的每个阳极的增益不均匀性。因此，可以更精确地计算γ射线的相互作用位置的优点。

5. 发明授权

US08808447B2 Pigment paint for an exterior material having good weather resistance and method for manufacturing same 有权
标题翻译：具有良好耐候性的外用材料用颜料漆及其制造方法
公开(公告)号：US08808447B2
公开(公告)日：2014-08-19
申请号：US14113324
申请日：2012-03-08
申请人： Jae-Il Jeong , Nam-Il Lee , Sang-Keun Park , Jin-Hyung Lee , Kwang-Choong Kang , Byung-Ki Choi , Kwang-Soo Lim , Kil-Wan Chang
发明人： Jae-Il Jeong , Nam-Il Lee , Sang-Keun Park , Jin-Hyung Lee , Kwang-Choong Kang , Byung-Ki Choi , Kwang-Soo Lim , Kil-Wan Chang
IPC分类号： C09C3/06 , C09C1/00 , C09C1/02 , C09C1/28 , C01G7/00 , C09C1/30 , C08K3/00 , C09C1/36
CPC分类号： C08K3/0075 , B82Y30/00 , C01G7/00 , C01G7/003 , C01P2004/04 , C01P2004/64 , C01P2006/60 , C08K3/10 , C09C1/30 , C09C1/36 , C09C3/06
摘要： The present invention relates to a pigment paint for an exterior material and to a method for manufacturing the same. The pigment paint comprises: a flake matrix, a first metal oxide layer coated on the upper portion of the transparent matrix, an oxide layer containing MgO—SiO2 coated on the upper portion of the first metal oxide layer, and a second metal oxide layer coated on the upper portion of the oxide layer. In order to ensure humidity resistance and weather resistance required for a lustrous pigment paint for exterior materials, a cerium layer and an aluminum oxide layer are further coated. Properties such as high luminance, high chromaticity, and high gloss, which could not be achieved using conventional techniques, can be achieved and a pigment paint having a multi-colored pearl luster can be provided.
摘要翻译：本发明涉及一种外用材料用颜料涂料及其制造方法。颜料涂料包括：薄片基质，涂覆在透明基体的上部的第一金属氧化物层，涂覆在第一金属氧化物层的上部的含有MgO-SiO 2的氧化物层和涂覆的第二金属氧化物层在氧化物层的上部。为了确保外部材料的光泽颜料涂料所需的耐湿性和耐候性，进一步涂覆铈层和氧化铝层。可以实现使用常规技术无法实现的诸如高亮度，高色度和高光泽度的性能，并且可以提供具有多色珍珠光泽的颜料涂料。

6. 发明申请

US20110192980A1 SYSTEM AND METHOD FOR COMPENSATING FOR ANODE GAIN NON-UNIFORMITY IN MULTI-ANODE POSITION SENSITIVE PHOTOMULTIPLIER TUBE 有权
标题翻译：用于补偿多阳性位置敏感光电管中ANODE GAIN非均匀性的系统和方法
公开(公告)号：US20110192980A1
公开(公告)日：2011-08-11
申请号：US12791988
申请日：2010-06-02
申请人： Jae Sung Lee , Chan Mi Lee , Sun Il Kwon , Mikiko Ito , Hyun Suk Yoon , Sang Keun Park , Seong Jong Hong , Dong Soo Lee
发明人： Jae Sung Lee , Chan Mi Lee , Sun Il Kwon , Mikiko Ito , Hyun Suk Yoon , Sang Keun Park , Seong Jong Hong , Dong Soo Lee
IPC分类号： G01T1/208
CPC分类号： G01T1/248 , G01T1/2018
摘要： The present invention relates to a system and method for compensating for anode gain non-uniformity in a Multi-anode Position Sensitive Photomultiplier Tube (PS-PMT), in which a compensation unit is disposed between the multi-anode position sensitive photomultiplier tube and a position detection circuit unit and configured to uniform a current signal inputted to the position detection circuit unit, thereby compensating for anode gain non-uniformity. In accordance with the present invention, the compensation unit for changing resistance is used. Accordingly, there is an advantage in that the gain non-uniformity of each of the anodes of the PS-PMT can be compensated for. Furthermore, the gain non-uniformity of each of the anodes of the PS-PMT is compensated for by changing resistance values of the variable resistances of the compensation unit. Accordingly, there is an advantage in that the interaction positions of gamma rays can be calculated more precisely.
摘要翻译：本发明涉及一种用于补偿多阳极位置敏感光电倍增管（PS-PMT）中的阳极增益不均匀性的系统和方法，其中补偿单元设置在多阳极位置敏感光电倍增管和位置检测电路单元，并且被配置为使输入到位置检测电路单元的电流信号均匀，从而补偿阳极增益不均匀。根据本发明，使用用于改变电阻的补偿单元。因此，可以补偿PS-PMT的每个阳极的增益不均匀性的优点。此外，通过改变补偿单元的可变电阻的电阻值来补偿PS-PMT的每个阳极的增益不均匀性。因此，可以更精确地计算γ射线的相互作用位置的优点。

7. 发明申请

US20060284686A1 Quadrature phase oscillator using complex coefficient filter 审中-公开
标题翻译：使用复系数滤波器的正交相位振荡器
公开(公告)号：US20060284686A1
公开(公告)日：2006-12-21
申请号：US11452719
申请日：2006-06-14
申请人： Si-Bum Jun , Sang-Keun Park , Woo-Yong Lee
发明人： Si-Bum Jun , Sang-Keun Park , Woo-Yong Lee
IPC分类号： H03L7/00
CPC分类号： H03B27/00
摘要： A quadrature phase oscillator in a Radio Frequency (RF) transceiver Integrated Circuit (IC) is provided. The quadrature phase oscillator includes a voltage controlled oscillator and a filter. The voltage controlled oscillator provides an oscillating frequency for modulation of a transmission/reception signal according to an applied voltage. The filter receives the oscillating frequency from the voltage controlled oscillator as an input, passes one of a negative frequency component of the input oscillating frequency and a positive frequency component of the input oscillating frequency, attenuates the other frequency component, generates an I (In phase) signal that is in phase with the input oscillating frequency and a Q (Quadrature phase) signal having a phase difference of 90° with the input oscillating frequency for the passed frequency component, and outputs the I signal and the Q signal.
摘要翻译：提供射频（RF）收发器集成电路（IC）中的正交相位振荡器。正交相位振荡器包括压控振荡器和滤波器。压控振荡器根据施加的电压提供用于调制发送/接收信号的振荡频率。滤波器接收来自压控振荡器的振荡频率作为输入，通过输入振荡频率的负频率分量和输入振荡频率的正频率分量之一，衰减另一频率分量，产生I（相位）信号和与输入振荡频率成90°相位差的Q（正交相位）信号，并输出I信号和Q信号。

8. 发明授权

US06845407B1 Semiconductor memory device having externally controllable data input and output mode 失效
标题翻译：具有外部可控数据输入和输出模式的半导体存储器件
公开(公告)号：US06845407B1
公开(公告)日：2005-01-18
申请号：US09621925
申请日：2000-07-24
申请人： Yong-Jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
发明人： Yong-Jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
IPC分类号： G01R31/26 , G01R31/28 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/413 , G11C11/417 , G11C16/06 , G11C17/00 , G11C17/18 , G11C29/14 , G06F3/00
CPC分类号： G11C7/1045 , G11C7/1078
摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.
摘要翻译：提供具有外部可控输入和输出模式的半导体存储器件。半导体存储器件包括第一和第二多个焊盘以及电连接到第一多个焊盘和第二多个焊盘的输入和输出模式设置电路，用于产生多个输入和输出模式信号。输入和输出模式设置电路切断从第一多个焊盘接收的信号，将每个输入和输出模式信号的电平控制在逻辑高电平和逻辑低电平，并设置输入和输出当在测试模式中将高于半导体存储器件的电源电压的电压施加到第二多个焊盘中的一个焊盘时，高电压不施加到第二多个焊盘，并且输入和输出模式设置电路将输入和输出模式信号的电平控制在逻辑高电平或逻辑低电平，从而将半导体存储器在正常操作期间具有响应于从所述多个焊盘接收的信号的一个输入和输出模式的装置。因此，可以从外部改变半导体存储器件的输入和输出模式。

9. 发明申请

US20050001244A1 Semiconductor memory device having externally controllable data input and output mode 失效
公开(公告)号：US20050001244A1
公开(公告)日：2005-01-06
申请号：US10900506
申请日：2004-07-27
申请人： Yong-jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
发明人： Yong-jin Park , Sang-keun Park , Hong Kim , Young-gu Kang
IPC分类号： G01R31/26 , G01R31/28 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/413 , G11C11/417 , G11C16/06 , G11C17/00 , G11C17/18 , G11C29/14 , G06G7/12
CPC分类号： G11C7/1045 , G11C7/1078
摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.

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