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1. 发明授权

US08949468B2 Method and system for time synchronization among systems using parallel sysplex links 有权
标题翻译：使用并行系统链路的系统之间的时间同步的方法和系统
公开(公告)号：US08949468B2
公开(公告)日：2015-02-03
申请号：US11247888
申请日：2005-10-11
申请人： Scott M. Carlson , David A. Elko , Richard K. Errickson
发明人： Scott M. Carlson , David A. Elko , Richard K. Errickson
IPC分类号： G06F15/16 , G06F9/54
CPC分类号： G06F1/12 , G06F1/14 , G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F9/5077 , G06F9/546 , G06F12/0238 , G06F2212/202 , H04J3/0667 , H04J3/0697 , H04L29/0854
摘要： Disclosed are a method of and system for providing time synchronization among first and second computer systems, where each of the computer systems includes hardware, operating system software and a layer of microcode operating between said hardware and said software. The method comprises the steps of using the microcode of the first computer system to provide a first timestamp, using the microcode of the second computer system to provide a second timestamp and a third timestamp, and using the microcode of the first computer system to provide a fourth timestamp. The method comprises the further steps of using the first, second, third and fourth timestamps to determine a timing difference between the first and second computer systems, and adjusting the timing among said first and second computer systems on the basis of said determined timing difference. Preferably, the first and second computer systems are connected together by a point-to-point link; and the first timestamp is sent from the first computer system to the second computer system, and the second and third timestamps are sent from the second computer system to the first computer system over that point-to-point link.
摘要翻译：公开了一种用于在第一和第二计算机系统之间提供时间同步的方法和系统，其中每个计算机系统包括在所述硬件和所述软件之间操作的硬件，操作系统软件和微代码层。该方法包括以下步骤：使用第一计算机系统的微码来提供第一时间戳，使用第二计算机系统的微码来提供第二时间戳和第三时间戳，并且使用第一计算机系统的微码来提供第一时间戳第四个时间戳。该方法还包括以下步骤：使用第一，第二，第三和第四时间标记来确定第一和第二计算机系统之间的定时差异，以及基于所确定的定时差来调整所述第一和第二计算机系统之间的定时。优选地，第一和第二计算机系统通过点对点链路连接在一起; 并且第一时间戳从第一计算机系统发送到第二计算机系统，并且第二和第三时间戳通过该点对点链路从第二计算机系统发送到第一计算机系统。

2. 发明授权

US07606965B2 Information handling system with virtualized I/O adapter ports 失效
标题翻译：具有虚拟化I / O适配器端口的信息处理系统
公开(公告)号：US07606965B2
公开(公告)日：2009-10-20
申请号：US11676555
申请日：2007-02-20
申请人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
发明人： Ugochukwu Charles Njoku , Frank W. Brice, Jr. , David Craddock , Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Donald W. Schmidt , Gustav E. Sittmann, III
IPC分类号： G06F13/00 , G06F13/14 , G06F9/455 , G06F3/00
CPC分类号： G06F13/4022 , G06F13/102
摘要： A communication port of a communications interface of an information handling system comprises a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then issued requesting the communications interface to virtualize the communication port. In response to the second command, one or more virtual switches are then configured to connect to the communication port, each virtual switch including a plurality of virtual ports, such that the one or more virtual switches are configured in a manner sufficient to support the number of images of virtual ports indicated by the obtained information. Thereafter, upon request via issuance of a third command, a logical link is established between one of the virtual ports of one of the virtual switches and a communicating element of the information handling system.
摘要翻译：信息处理系统的通信接口的通信端口包括多个虚拟端口。发出第一命令以获得指示可由通信接口支持的虚拟端口的图像数量的信息。然后发出请求通信接口虚拟通信端口的第二命令。响应于第二命令，一个或多个虚拟交换机然后被配置为连接到通信端口，每个虚拟交换机包括多个虚拟端口，使得一个或多个虚拟交换机被配置为足以支持数量由所获得的信息指示的虚拟端口的图像。此后，根据通过发出第三命令的请求，在一个虚拟交换机的虚拟端口之一和信息处理系统的通信元件之间建立逻辑链路。

3. 发明申请

US20090217270A1 NEGATING INITIATIVE FOR SELECT ENTRIES FROM A SHARED, STRICTLY FIFO INITIATIVE QUEUE 有权
标题翻译：从一个共享的，严格的主动队列排除选择条件的主动
公开(公告)号：US20090217270A1
公开(公告)日：2009-08-27
申请号：US12051628
申请日：2008-03-19
申请人： Richard K. Errickson , Geoffrey A. Crew , Welela Haileselaissie , Robert M. Whalen, JR.
发明人： Richard K. Errickson , Geoffrey A. Crew , Welela Haileselaissie , Robert M. Whalen, JR.
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F2209/548
摘要： A computer program product, apparatus and method for negating initiative for select entries from a shared, strictly FIFO initiative queue in a multi-tasking multi-processor environment. An exemplary embodiment includes a computer program product for negating initiative for select entries from a shared initiative queue in a multi-tasking multi-processor environment, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including identifying an element within the environment that has failed and recovered, not removing the element from the shared initiative queue and entering a boundary element entry into the shared initiative queue.
摘要翻译：一种计算机程序产品，装置和方法，用于在多任务多处理器环境中从共享的严格FIFO主动队列中取消选择条目的主动性。一个示例性实施例包括一种计算机程序产品，用于在多任务多处理器环境中从共享主动队列中拒绝主动选择条目的计算机程序产品，该计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路，用于执行包括识别环境中已经失败和恢复的元素的方法，而不是从共享主动队列中移除元素并且将边界元素条目输入到共享主动队列中。

4. 发明授权

US07581021B2 System and method for providing multiple virtual host channel adapters using virtual switches 有权
标题翻译：使用虚拟交换机提供多个虚拟主机通道适配器的系统和方法
公开(公告)号：US07581021B2
公开(公告)日：2009-08-25
申请号：US11100846
申请日：2005-04-07
申请人： Richard K. Errickson , David Craddock , Thomas A. Gregg , Donald W. Schmidt , Jeffrey M. Turner , Bruce M. Walk
发明人： Richard K. Errickson , David Craddock , Thomas A. Gregg , Donald W. Schmidt , Jeffrey M. Turner , Bruce M. Walk
IPC分类号： G06F15/173
CPC分类号： H04L49/35 , H04L49/30 , H04L49/358 , H04L49/70 , H04L67/1097
摘要： A processor node of a network is provided which includes one or more processors and a virtualized channel adapter. The virtualized channel adapter is operable to reference a table to determine whether a destination of the communication is supported by the virtualized channel adapter. When the destination is supported for routing via hardware, the virtualized channel adapter is operable to route the communication via hardware to at least one of a physical port and a logical port of the virtualized channel adapter. Otherwise, when the destination is not supported for routing via hardware, the virtualized channel adapter is operable to route the communication via firmware to a virtual port of the virtualized channel adapter. A corresponding method and a recording medium having information recorded thereon for performing such method are also provided herein.
摘要翻译：提供网络的处理器节点，其包括一个或多个处理器和虚拟通道适配器。虚拟化通道适配器可操作以引用表以确定通信的目的地是否由虚拟化通道适配器支持。当目的地被支持通过硬件进行路由时，虚拟化信道适配器可操作以经由硬件将通信路由到虚拟化信道适配器的物理端口和逻辑端口中的至少一个。否则，当目的地不支持通过硬件进行路由时，虚拟化信道适配器可操作地将通过固件的通信路由到虚拟化信道适配器的虚拟端口。本文还提供了相应的方法和记录介质，用于执行这种方法。

5. 发明授权

US07234037B2 Memory mapped Input/Output operations 有权
标题翻译：内存映射输入/输出操作
公开(公告)号：US07234037B2
公开(公告)日：2007-06-19
申请号：US10723044
申请日：2003-11-25
申请人： Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
发明人： Richard K. Errickson , Mark S. Farrell , Charles W. Gainey, Jr. , Thomas A. Gregg , Carol B. Hernandez , Donald W. Schmidt
IPC分类号： G06F9/34
CPC分类号： G06F12/1475 , G06F9/30003 , G06F9/342 , G06F12/063
摘要： A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with the definition(s) of the z/Architecture; and wherein a process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
摘要翻译：一种向备用地址空间执行存储器映射输入输出操作的方法，包括：根据z / Architecture的定义，建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第一指令以存储数据; 建立指向与适配器相关联的第一存储器映射输入输出备用地址空间的第二指令，以根据z / Architecture的定义加载数据; 并且其中，处理发出所述第一指令和所述第二指令中的至少一个，从而使得所述存储器和所述负载中的至少一个与所述第一备用地址空间一起执行。

6. 发明授权

US06671733B1 Internal parallel system channel 有权
标题翻译：内部并行系统通道
公开(公告)号：US06671733B1
公开(公告)日：2003-12-30
申请号：US09534679
申请日：2000-03-24
申请人： Richard K. Errickson , Ambrose A. Verdibello, Jr.
发明人： Richard K. Errickson , Ambrose A. Verdibello, Jr.
IPC分类号： G06F1750
CPC分类号： H04L29/06 , H04L69/32 , Y10S707/99945
摘要： A method and apparatus that provide connectivity in a computer network environment that includes a plurality of nodes, interface links and at least one central electronic complex divided into one or more physical and or virtual sub-environments. A first control program is provided in the central electronic complex in order to establish a first command process layer and a first transfer process layer within this first control program for handling data. The first command process layer is then linked to the first transfer process layer in this control program. A second control program is also provided in the central electronic complex in order to establish a second command process layer and a second transfer process layer within this second control program for handling data. The second command process layer is also linked to the second transfer layer in said second control program. Ultimately a link is emulated between the first transfer process layer and the second transfer process layer; and a physical interface is provided between the first transfer process layer and the second transfer process layer without affecting any of the logical interface(s) between the transfer process layers.
摘要翻译：在计算机网络环境中提供连接性的方法和装置，其包括多个节点，接口链路以及分成一个或多个物理和/或虚拟子环境的至少一个中央电子综合体。在中央电子综合体中提供第一控制程序，以便在该第一控制程序内建立第一命令处理层和第一传送处理层以处理数据。然后，第一命令处理层被链接到该控制程序中的第一传送处理层。在中央电子综合体中还提供第二控制程序，以在该第二控制程序内建立第二命令处理层和第二传送处理层来处理数据。第二命令处理层也与所述第二控制程序中的第二传送层相连。最终在第一转移处理层和第二转移处理层之间仿真一个链接; 并且在第一传送处理层和第二传送处理层之间提供物理接口，而不会影响传送处理层之间的任何逻辑接口。

7. 发明授权

US08432793B2 Managing recovery of a link via loss of link 有权
标题翻译：通过链接丢失来管理链接的恢复
公开(公告)号：US08432793B2
公开(公告)日：2013-04-30
申请号：US12051630
申请日：2008-03-19
申请人： Richard K. Errickson , Leonard W. Helmer, Jr. , John S. Houston
发明人： Richard K. Errickson , Leonard W. Helmer, Jr. , John S. Houston
IPC分类号： H04L12/26
CPC分类号： G06F9/546 , G06F2209/548
摘要： A computer program product, apparatus and method for managing recovery of a link in a multi-tasking multi-processor environment. An exemplary embodiment includes shutting off timers for a failed channel associated with the communications link, storing a loss of link condition in a data structure, disabling communications on the failed channel and sending an external notification of the loss of link condition.
摘要翻译：一种用于管理多任务多处理器环境中的链路的恢复的计算机程序产品，装置和方法。示例性实施例包括关闭与通信链路相关联的失败信道的定时器，将数据结构中的链路状况丢失，禁用在故障信道上的通信并发送链路状况丢失的外部通知。

8. 发明授权

US08065279B2 Performance neutral heartbeat for a multi-tasking multi-processor environment 失效
标题翻译：多任务多处理器环境的性能中立心跳
公开(公告)号：US08065279B2
公开(公告)日：2011-11-22
申请号：US12036983
申请日：2008-02-25
申请人： Richard K. Errickson , Leornard W. Helmer, Jr. , John S. Houston
发明人： Richard K. Errickson , Leornard W. Helmer, Jr. , John S. Houston
IPC分类号： G06F17/00
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/0757 , H04L43/0811 , H04L43/10 , H04L69/40
摘要： A computer program product, apparatus and method for providing a performance neutral heartbeat in a computer communication system, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including maintaining a send flag, maintaining a receive flag, determining that a heartbeat timer has activated, checking a state of the send flag to determine if packets have been sent since a prior heartbeat timer activation and checking a state of the receive flag to determine if packets have been received since a prior heartbeat timer activation.
摘要翻译：一种用于在计算机通信系统中提供性能中立的心跳的计算机程序产品，装置和方法，所述计算机程序产品包括由处理电路可读的有形存储介质，并且存储由处理电路执行以执行包括维持发送标志，维持接收标志，确定心跳定时器已经被激活，检查发送标志的状态，以确定是否已经发送了自从之前的心跳定时器激活并且检查接收标志的状态以确定分组是否已被自从以前的心跳定时器激活接收。

9. 发明授权

US07797414B2 Establishing a logical path between servers in a coordinated timing network 有权
标题翻译：在协调的定时网络中建立服务器之间的逻辑路径
公开(公告)号：US07797414B2
公开(公告)日：2010-09-14
申请号：US11876272
申请日：2007-10-22
申请人： Scott M. Carlson , Dennis J. Dahlen , Richard K. Errickson
发明人： Scott M. Carlson , Dennis J. Dahlen , Richard K. Errickson
IPC分类号： G06F15/173
CPC分类号： H04L67/1095 , G06F1/12 , G06F1/14 , H04L69/28
摘要： A technique for establishing a logical path between two servers in a coordinated timing network of a processing environment is provided. The technique includes the exchange of command and response message pairs by a server and an attached server, via a physical link. The server transmits a command message to an attached server to establish a server-time-protocol (STP) logical path and receives a response from the attached server. The technique also includes the server receiving a request transmitted by the attached server to establish an STP logical path to the server and transmitting a response to the attached server's request. A logical path between the server and the attached server is established if the attached server's response indicates that the server's request was accepted by the attached server and if the server's response indicates that the attached server's request was accepted by the server.
摘要翻译：提供了一种用于在处理环境的协调定时网络中建立两个服务器之间的逻辑路径的技术。该技术包括通过物理链路由服务器和连接的服务器交换命令和响应消息对。服务器向连接的服务器发送命令消息以建立服务器时间协议（STP）逻辑路径，并从所附加的服务器接收响应。该技术还包括服务器接收由连接的服务器发送的请求以建立到服务器的STP逻辑路径并且发送对所附加的服务器的请求的响应。如果连接的服务器的响应指示服务器的请求被连接的服务器接受并且服务器的响应指示服务器接受了附加服务器的请求，则建立服务器和附加服务器之间的逻辑路径。

10. 发明申请

US20090217291A1 PERFORMANCE NEUTRAL HEARTBEAT FOR A MULTI-TASKING MULTI-PROCESSOR ENVIRONMENT 失效
标题翻译：性能中性心脏多用途多中心环境
公开(公告)号：US20090217291A1
公开(公告)日：2009-08-27
申请号：US12036983
申请日：2008-02-25
申请人： Richard K. Errickson , Leornard W. Helmer, JR. , John S. Houston
发明人： Richard K. Errickson , Leornard W. Helmer, JR. , John S. Houston
IPC分类号： G06F9/46
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/0757 , H04L43/0811 , H04L43/10 , H04L69/40
摘要： A computer program product, apparatus and method for providing a performance neutral heartbeat in a computer communication system, the computer program product including a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method including maintaining a send flag, maintaining a receive flag, determining that a heartbeat timer has activated, checking a state of the send flag to determine if packets have been sent since a prior heartbeat timer activation and checking a state of the receive flag to determine if packets have been received since a prior heartbeat timer activation.
摘要翻译：一种用于在计算机通信系统中提供性能中立的心跳的计算机程序产品，装置和方法，所述计算机程序产品包括由处理电路可读的有形存储介质，并且存储由处理电路执行以执行包括维持发送标志，维持接收标志，确定心跳定时器已经被激活，检查发送标志的状态，以确定是否已经发送了自从之前的心跳定时器激活并且检查接收标志的状态以确定分组是否已被自从以前的心跳定时器激活接收。

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