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1. 发明授权

US06320808B1 Memory read amplifier circuit with high current level discrimination capacity 有权
标题翻译：具有高电流电平鉴别能力的存储器读取放大器电路
公开(公告)号：US06320808B1
公开(公告)日：2001-11-20
申请号：US09686632
申请日：2000-10-11
申请人： Antonino Conte , Maurizio Gaibotti
发明人： Antonino Conte , Maurizio Gaibotti
IPC分类号： G11C700
CPC分类号： G11C7/067 , G11C7/062 , G11C2207/063
摘要： A memory read amplifier circuit includes at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line. A first cascode circuit is connected between a supply voltage and the memory cell for providing a first current to the memory cell. The memory read amplifier circuit also includes at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line. A second cascode circuit is connected between the supply voltage and the reference memory cell for providing a second current to the reference memory cell. A differential comparator circuit having a first input is connected to the control terminal of the first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the control terminal of the second cascode circuit for receiving a second voltage based upon the second current. The differential comparator circuit compares the first and second voltages for providing a logic value relegates to a state of the memory cell to be read.
摘要翻译：存储器读取放大器电路包括要被读取的至少一个存储器单元和与其连接的位线，连接到位线的第一预充电放大器电路。第一级联电路连接在电源电压和存储单元之间，用于向存储单元提供第一电流。存储器读取放大器电路还包括至少一个参考存储单元和连接到其上的参考位线，以及连接到参考位线的第二预充电放大器电路。第二级联电路连接在电源电压和参考存储单元之间，用于向参考存储单元提供第二电流。具有第一输入的差分比较器电路连接到第一共源共栅电路的控制端，用于基于第一电流接收第一电压，第二输入连接到第二共源共栅电路的控制端，用于接收第二电压在第二个电流。差分比较器电路比较第一和第二电压以提供降低要读取的存储器单元的状态的逻辑值。

2. 发明授权

US06198672B1 Voltage phase generator with increased driving capacity 有权
标题翻译：具有增加驱动能力的电压相位发生器
公开(公告)号：US06198672B1
公开(公告)日：2001-03-06
申请号：US09257684
申请日：1999-02-26
申请人： Carmela Calafato , Maurizio Gaibotti
发明人： Carmela Calafato , Maurizio Gaibotti
IPC分类号： G11C700
CPC分类号： G11C5/145 , G11C5/14 , G11C16/08
摘要： A voltage phase generator that generates a normal voltage phase, a negated normal voltage phase, a boosted voltage phase, and a negated boosted voltage phase. The voltage phase generator includes a first driver circuit that supplies the normal voltage phase to a first output node, and a second driver circuit that supplies the negated normal voltage phase to a second output node. The first and second driver circuits are driven by additional voltage phases that have a boosted voltage. In one preferred embodiment, each of the driver circuits includes a pull-up connected between a supply voltage and one of the output nodes, and a pull-down connected between ground and the one output node. Additionally, the present invention provides a voltage boosting circuit that includes a booster circuit and a voltage phase generator. The booster circuit receives four voltage phases and generates a boosted voltage, and the voltage phase generator generates the four voltage phases and additional voltage phases that have a boosted voltage. The additional voltage phases drive driver circuits that supply the normal voltage phase and the negated normal voltage phase to the booster circuit. In a preferred embodiment, the voltage boosting circuit is integrated in a low supply voltage circuit device.
摘要翻译：电压相位发生器，其产生正常电压相位，正负电压相位，升压电压相位和否定升压电压相位。电压相位发生器包括将正常电压相位提供给第一输出节点的第一驱动器电路和将否定正常电压相位提供给第二输出节点的第二驱动器电路。第一和第二驱动电路由具有升压电压的附加电压相驱动。在一个优选实施例中，每个驱动器电路包括连接在电源电压和输出节点之一之间的上拉电路以及连接在地和一个输出节点之间的下拉电路。另外，本发明提供一种升压电路，其包括升压电路和电压相位发生器。升压电路接收四个电压相位并产生升压电压，并且电压相位发生器产生四个电压相位和具有升压电压的附加电压相位。额外的电压相驱动向升压电路提供正常电压相位和否定正常电压相位的驱动电路。在优选实施例中，升压电路集成在低电源电压装置中。

3. 发明授权

US6130844A Low consumption boosted voltage driving circuit 有权
标题翻译：低功耗升压电压驱动电路
公开(公告)号：US6130844A
公开(公告)日：2000-10-10
申请号：US257682
申请日：1999-02-26
申请人： Tommaso Zerilli , Maurizio Gaibotti
发明人： Tommaso Zerilli , Maurizio Gaibotti
IPC分类号： G11C8/08 , G11C7/00
CPC分类号： G11C8/08
摘要： A boosted voltage driving circuit includes an inverter circuit with positive feedback and a selective breaking circuit. The selective breaking circuit disconnects the positive feedback from the output load during an operation phase of the boosted voltage driving circuit in order to reduce energy consumption. In a preferred embodiment, the boosted voltage driving circuit is the final stage of a decoder circuit for selecting and deselecting a line or column of a memory array, and the positive feedback is disconnected during a deselection phase in which the line or column is deselected. The present invention also provides a boosted voltage driving circuit that includes first, second, and third transistors and a selective breaking circuit. The first transistor is connected between a supply voltage and an output node, the second transistor is connected between the output node and ground, and the third transistor is connected between the supply voltage and the gate of the first transistor. Further, the selective breaking circuit is connected between the output node and the gate of the third transistor to disconnect the gate of the third transistor from the output node during an operation phase of the boosted voltage driving circuit.
摘要翻译：升压电压驱动电路包括具有正反馈的反相器电路和选择性分断电路。选择性分断电路在升压电压驱动电路的运行阶段将正反馈与输出负载断开，以便降低能耗。在优选实施例中，升压电压驱动电路是用于选择和取消选择存储器阵列的行或列的解码器电路的最后一级，并且在取消选择行或列的取消选择阶段中断开正反馈。本发明还提供一种包括第一，第二和第三晶体管和选择性分断电路的升压电压驱动电路。第一晶体管连接在电源电压和输出节点之间，第二晶体管连接在输出节点和地之间，第三晶体管连接在电源电压和第一晶体管的栅极之间。此外，选择性分断电路连接在第三晶体管的输出节点和栅极之间，以在升压电压驱动电路的操作阶段期间将第三晶体管的栅极与输出节点断开。

4. 发明授权

US5821791A Low-consumption and high-density D flip-flop circuit implementation particularly for standard cell libraries 失效
标题翻译：低消耗和高密度D触发器电路特别适用于标准单元库
公开(公告)号：US5821791A
公开(公告)日：1998-10-13
申请号：US730699
申请日：1996-10-11
申请人： Maurizio Gaibotti , Francesco Adduci
发明人： Maurizio Gaibotti , Francesco Adduci
IPC分类号： H03K3/3562 , H03K3/289
CPC分类号： H03K3/35625
摘要： A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.
摘要翻译：公开并要求保护低功耗和高密度D触发器电路，特别是对于包括主器件部分和从器件部分的标准单元库。主部分包括主锁存结构，将主锁存器结构连接到两个电源电压中的一个的主耦合电路，以及用于将数据应用于触发器的输入耦合电路。从部分包括直接插入在两个电源电压之间的从锁存结构，以及将从锁存结构连接到主锁存结构的从耦合电路。通过扩大输入耦合电路中的晶体管的源极面积，实现本发明的D触发器电路实现所需的晶体管的数量被最小化，这导致大的寄生电容并确保主锁存器的最佳操作。此外，从锁存结构中的晶体管具有非最小栅极长度。此外，单个时钟信号用于启用主和从部分。使用无需本地再生的单个时钟信号与最小化所需组件数量的能力有助于实现更高的集成电路密度并降低功耗。

5. 发明授权

US06650153B2 Generator circuit for voltage ramps and corresponding voltage generation method 有权
公开(公告)号：US06650153B2
公开(公告)日：2003-11-18
申请号：US10033711
申请日：2001-12-28
申请人： Tommaso Zerilli , Maurizio Gaibotti
发明人： Tommaso Zerilli , Maurizio Gaibotti
IPC分类号： H03K406
CPC分类号： H03K17/163 , H03K4/00
摘要： A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

6. 发明授权

US06466059B1 Sense amplifier for low voltage memories 失效
标题翻译：用于低电压存储器的感应放大器
公开(公告)号：US06466059B1
公开(公告)日：2002-10-15
申请号：US09249834
申请日：1999-02-12
申请人： Maurizio Gaibotti , Nicolas Demange
发明人： Maurizio Gaibotti , Nicolas Demange
IPC分类号： G01R1900
CPC分类号： G11C16/24 , G11C7/062 , G11C7/12 , G11C16/28
摘要： A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier. Another embodiment provides a sense amplifier that includes a first current mirror having one branch coupled to a cell array bit line, and a second current mirror having a branch coupled to both a reference bit line and another branch of the first current mirror. In one preferred embodiment, the second current mirror mirrors a predetermined current that is generated outside of the sense amplifier. A method for sensing the current of a memory cell in a memory device is also provided.
摘要翻译：一种耦合到参考位线和至少一个单元阵列位线的读出放大器。读出放大器包括放大级和电流电压转换电路，其比较来自参考位线的参考电流和来自单元阵列位线的单元电流。电流 - 电压转换电路包括用于设置参考位线和单元阵列位线上的预定电压的电压设置电路，用于参考位线和单元阵列位线的负载电路以及用于镜像参考电流的电流镜电路电流和电池电流进入放大级。用于参考位线的负载电路和用于参考电流的电流镜电路是不同的电路，并且用于参考位线的负载电路包括反映在读出放大器外部产生的预定电流的晶体管。另一实施例提供了一种读出放大器，其包括具有耦合到单元阵列位线的一个分支的第一电流镜和具有耦合到第一电流镜的另一分支的分支的第二电流镜。在一个优选实施例中，第二电流镜反映在读出放大器外部产生的预定电流。还提供了用于感测存储器件中的存储单元的电流的方法。

7. 发明授权

US6064594A Voltage boosting circuit for generating boosted voltage phases 有权
标题翻译：用于产生升压电压相的升压电路
公开(公告)号：US6064594A
公开(公告)日：2000-05-16
申请号：US258224
申请日：1999-02-26
申请人： Carmela Calafato , Maurizio Gaibotti
发明人： Carmela Calafato , Maurizio Gaibotti
IPC分类号： G11C5/14 , G11C8/08 , G11C7/00
CPC分类号： G11C8/08 , G11C5/145
摘要： A voltage boosting circuit for use in an integrated circuit having at least four driving voltage phases that include first and second voltage phases with amplitudes substantially equal to the supply voltage, and first and second boosted voltage phases. The voltage boosting circuit includes an input that receives the first or second voltage phase, an output that supplies the first or second boosted voltage phase, and a charge node that is coupled to the input. Additionally, a supply voltage precharge circuit precharges the charge node, and an additional transistor is connected between the supply voltage and the charge node. The additional transistor is driven by a voltage with a greater amplitude than the supply voltage so that the charge node is precharged up to the supply voltage and the first or second boosted voltage phase that is output by the voltage boosting circuit reaches an amplitude equal to substantially twice the supply voltage. In one preferred embodiment, the additional transistor is an N-channel transistor, the voltage that drives the additional transistor is the second boosted voltage phase, and the first boosted voltage phase is supplied at the output of the voltage boosting circuit.
摘要翻译：一种用于具有至少四个驱动电压相位的集成电路的升压电路，所述驱动电压相包括幅度基本上等于电源电压的第一和第二电压相位以及第一和第二升压电压相位。升压电路包括接收第一或第二电压相位的输入端，提供第一或第二升压电压相位的输出端以及耦合到输入端的充电节点。此外，电源电压预充电电路对电荷节点进行预充电，并且附加晶体管连接在电源电压和充电节点之间。附加晶体管由具有比电源电压更大的幅度的电压驱动，使得充电节点被预充电到电源电压，并且由升压电路输出的第一或第二升压电压相位达到等于基本上的幅度两倍电源电压。在一个优选实施例中，附加晶体管是N沟道晶体管，驱动附加晶体管的电压是第二升压电压相位，并且在升压电路的输出处提供第一升压电压相位。

8. 发明授权

US5225724A Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit 失效
标题翻译：具有单个扫描时钟的扫描路径类型和用于集成电路的单个输出相的操作分析设备
公开(公告)号：US5225724A
公开(公告)日：1993-07-06
申请号：US781360
申请日：1991-10-22
申请人： Flavio Scarra' , Maurizio Gaibotti
发明人： Flavio Scarra' , Maurizio Gaibotti
IPC分类号： G01R31/3183 , G01R31/3185 , G06F11/22 , G06F15/78 , H01L21/66 , H01L21/822 , H01L27/04
CPC分类号： G01R31/318552
摘要： The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.

9. 发明授权

US06927441B2 Variable stage charge pump 有权
标题翻译：可变级电荷泵
公开(公告)号：US06927441B2
公开(公告)日：2005-08-09
申请号：US10050427
申请日：2002-01-15
申请人： Domenico Pappalardo , Maurizio Gaibotti , Gaetano Palumbo , Antonino Conte , Stefano Lo Giudice
发明人： Domenico Pappalardo , Maurizio Gaibotti , Gaetano Palumbo , Antonino Conte , Stefano Lo Giudice
IPC分类号： H02J7/00 , H02M3/07 , H01L27/10 , H02M3/18
CPC分类号： H02M3/07 , H02M2003/077
摘要： A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.
摘要翻译：可变电荷泵包含几个单独的简单电荷泵，每个具有泵浦电容器和开关机构。此外，开关网络耦合到各个电荷泵，使得电荷泵中的不同线路可以以串行模式或并行模式（或混合串行和并行模式）连接在一起以匹配输出负载的需要。随着输出负载的变化需要，开关网络容易改变以提供必要的驱动能力。

10. 发明授权

US06420926B2 CMOS technology voltage booster 有权
标题翻译： CMOS技术升压器
公开(公告)号：US06420926B2
公开(公告)日：2002-07-16
申请号：US09738890
申请日：2000-12-15
申请人： Luca Lo Coco , Maurizio Gaibotti
发明人： Luca Lo Coco , Maurizio Gaibotti
IPC分类号： G05F302
CPC分类号： G11C5/145
摘要： A CMOS technology voltage booster having plurality of charge-pump stages cascade connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node, with at least one transistor connected therebetween that has its control terminal connected to an internal circuit node of the same stage and applied one of the phases. This voltage booster further includes a pair of additional circuit elements for transferring, onto the internal node, a potential exceeding the voltage at the input node by at least one threshold. A first of the additional elements is essentially a MOS transistor having its control terminal connected to the control terminal of that transistor that is connected between the input and the output of the stage, while the second additional element is an auxiliary capacitor having one end connected directly to the first additional element and connected to the internal node through a transistor.
摘要翻译：一种具有多个电荷泵级联的CMOS技术电压升压器，其级联连接在一起并被多个相位驱动，每个级具有端接输入节点和端接输出节点，其中连接有至少一个晶体管，其控制端连接到同一级的内部电路节点并应用其中一个阶段。该电压升压器还包括一对附加电路元件，用于将超过输入节点上的电压的电势传送至内部节点至少一个阈值。附加元件中的第一个本质上是MOS晶体管，其控制端连接到该晶体管的控制端子，该控制端子连接在该级的输入和输出端之间，而第二附加元件是一端直接连接的辅助电容器到第一个附加元件并通过晶体管连接到内部节点。

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