专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06320469B1 Lock detector for phase-locked loop 有权
标题翻译：锁相环锁定检测器
公开(公告)号：US06320469B1
公开(公告)日：2001-11-20
申请号：US09504397
申请日：2000-02-15
申请人： Donald H. Friedberg , Dale Harvey Nelson , Lai Q. Pham
发明人： Donald H. Friedberg , Dale Harvey Nelson , Lai Q. Pham
IPC分类号： H03L7095
CPC分类号： H03L7/095 , H03L7/18 , Y10S331/02
摘要： A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.
摘要翻译：一种用于检测参考信号和PLL电路的反馈信号之间的锁定的方法和锁定检测器。在由参考信号定义的连续测试间隔期间，对反馈信号的多个时钟周期进行计数。反馈比较器确定给定测试间隔期间反馈信号的时钟周期数是否在预期范围内。在指示锁定之前，根据预期的范围确定，每个测试间隔后，限定计数器递增或复位。如果所述鉴定计数器超过限定阈值，则提供指示已经实现锁定的锁定指示信号。

2. 发明授权

US06725305B1 Method and apparatus for using a bus as a data storage node 有权
标题翻译：一种使用总线作为数据存储节点的方法和装置
公开(公告)号：US06725305B1
公开(公告)日：2004-04-20
申请号：US09474412
申请日：1999-12-29
申请人： Hyun Lee , David W. Potter , Lai Q. Pham
发明人： Hyun Lee , David W. Potter , Lai Q. Pham
IPC分类号： G06F1300
CPC分类号： G06F13/4077
摘要： The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased by eliminating the use of active bus keepers and null cycles. Instead, a two phase clock is used, the bus drivers drive data onto the bus during the first phase of the clock and are turned off at the beginning of the second phase of the bus clock. The receiving device latches the data during the second phase of the bus clock. Accordingly, there is no need for a null cycle or a bus keeper circuit, yet there is no bus contention between consecutive drivers nor is there a floating node condition.
摘要翻译：本发明是一种通过利用总线的固有存储容量来在总线上动态地保持有效数据逻辑电平的方法和装置。通过消除使用有效的总线管理器和空循环来增加总线速度。相反，使用两相时钟，总线驱动器在时钟的第一阶段将数据驱动到总线上，并且在总线时钟的第二阶段开始时被关断。接收装置在总线时钟的第二阶段期间锁存数据。因此，不需要空循环或总线保护电路，但是在连续驱动器之间没有总线争用，也没有浮动节点条件。

3. 发明授权

US07174475B2 Method and apparatus for distributing a self-synchronized clock to nodes on a chip 有权
标题翻译：将自同步时钟分配给芯片上的节点的方法和装置
公开(公告)号：US07174475B2
公开(公告)日：2007-02-06
申请号：US09785604
申请日：2001-02-16
申请人： Hyun Lee , Han Nguyen , Lai Q. Pham
发明人： Hyun Lee , Han Nguyen , Lai Q. Pham
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A method and apparatus are disclosed for dynamically reducing clock skew among various nodes on an integrated circuit. The disclosed clock skew reduction technique dynamically estimates the clock delay to each node and inserts a corresponding delay for each node such that the clock signals arriving at each node are all in phase with a global clock (or 180° out of phase). Delays attributable to both the wire RC delays and the clock buffer delays are addressed. A feedback path for the clock signal associated with each node allows the round trip travel time of the clock signal to be estimated. When the length of the feedback path matches the length of the primary clock path, the clock skew present at the corresponding node can be estimated as fifty percent (50%) of the round trip delay time. Dynamic adjustments to the delay control circuit are permitted as operating conditions shift. Clock signals arriving at individual nodes on the integrated circuit remain in phase with the global PLL clock (PCK), regardless of variations in the operating voltage or temperature (or both).
摘要翻译：公开了用于动态地减少集成电路中的各个节点之间的时钟偏移的方法和装置。所公开的时钟偏移减少技术动态地估计到每个节点的时钟延迟，并为每个节点插入相应的延迟，使得到达每个节点的时钟信号都与全局时钟（或相位相差180°）同相。解决了归因于有线RC延迟和时钟缓冲器延迟的延迟。与每个节点相关联的时钟信号的反馈路径允许估计时钟信号的往返行程时间。当反馈路径的长度与主时钟路径的长度匹配时，存在于相应节点处的时钟偏差可以估计为往返延迟时间的百分之五十（50％）。随着操作条件的变化，允许对延迟控制电路进行动态调整。到达集成电路各个节点的时钟信号与全局PLL时钟（PCK）保持同步，无论工作电压或温度（或两者）的变化如何。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式