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    • 1. 发明授权
    • Synchronizing system in digital communication line
    • 数字通信线路同步系统
    • US5228035A
    • 1993-07-13
    • US784588
    • 1991-10-29
    • Akira HiratoYuji KondoHideharu OmoriNaoyuki YamaguchiKoichi IchimuraYoshihiro Kawata
    • Akira HiratoYuji KondoHideharu OmoriNaoyuki YamaguchiKoichi IchimuraYoshihiro Kawata
    • H04L7/00H04J3/06H04L7/033H04Q11/04
    • H04J3/0688H04J3/0602H04L7/0331H04Q11/04
    • A synchronizing system in a digital communication line comprises a plurality of local switches for storing at least one digital line and monitoring a first piece of busy information when a clock source is already present, the local switches, if a first new clock source occurs while the first busy information is indicating no busy state, being capable of transmitting a master right request to turn the busy information to the busy state and to specify the first new clock source as a master clock and, on receiving a master right specification with respect to the master right request, being capable of outputting the first new clock source as the master clock; and a master switch connected to the plurality local switches in a star manner, by a link transmission line for transmitting control information including the master clock, master right request and master right specification, for monitoring a second piece of busy information indicating a busy state, the master switch, if a second new clock source occurs while the second busy information is indicating no busy state, being capable of transmitting the second new clock source as a master clock and, if the second new clock source competes with the first new clock source in the local switches that has output the master right request, being capable of arbitrating the competition between the first and second new clock sources and selecting one of the clock sources to turn the busy information to the busy state and, if the first clock source is selected, outputting the master right specification to the local switches that have transmitted the master right request.
    • 数字通信线路中的同步系统包括多个本地交换机,用于存储至少一个数字线路,并且当时钟源已经存在时监视第一条忙信息,本地交换机如果在第一新时钟源发生时 首先忙信息指示不处于忙状态,能够发送主请求以将忙信息转换到忙状态,并且将第一新时钟源指定为主时钟,并且在接收到关于第 能够将第一个新时钟源作为主时钟输出; 以及以星形方式连接到多个本地交换机的主交换机,通过用于发送包括主时钟,主权限请求和主权限规定的控制信息的链路传输线,用于监视指示忙碌状态的第二忙碌信息, 主开关,如果在第二忙信息指示无忙状态时发生第二新时钟源,则能够将第二新时钟源作为主时钟发送,并且如果第二新时钟源与第一新时钟源竞争 在输出主权请求的本地交换机中,能够对第一和第二新时钟源之间的竞争进行仲裁,并选择其中一个时钟源将繁忙信息转为忙状态,如果第一个时钟源为 选择,将主权限规范输出到已发送主权请求的本地交换机。
    • 2. 发明授权
    • Decision feedback equalizer
    • 决策反馈均衡器
    • US06996169B2
    • 2006-02-07
    • US09866954
    • 2001-05-29
    • Masaru MiyamotoKoichi IchimuraAtsushi Fujimoto
    • Masaru MiyamotoKoichi IchimuraAtsushi Fujimoto
    • H03H7/30
    • H04L25/03057H04L25/0212H04L25/062H04L25/4923H04L2025/03401H04L2025/03503
    • A decision feed back equalizer provides two feedback routines for one symbol-preceding decided data. The signal space is separated into decidable areas and uncertainty areas. Within each of decidable area the distance between any point and the signal point is small. Within each uncertainty area the distance between any point and the signal point is large. If the symbol-preceding equalized signal is in a decidable area, the piece of decided data is fed back, as it is presumed to be correct. If the symbol-preceding equalized signal exists in an uncertainty area, the piece of decided data is not fed back, as it is presumed to be in error. Here the one piece data is selected from all the predicted symbol-preceding decided data so that the instant equalized data is now in the decidable area. This piece of decided data is now fed back.
    • 决策反馈均衡器为一个符号前面决定的数据提供两个反馈程序。 信号空间分为可判定区域和不确定区域。 在每个可判定区域内,任意点与信号点之间的距离很小。 在每个不确定区域内,任何点与信号点之间的距离较大。 如果符号前置的均衡信号在可判定区域中,则判断数据被反馈,因为它被认为是正确的。 如果符号前面的均衡信号存在于不确定区域中,则判定数据被反馈,因为它被认为是错误的。 这里,从所有预测的符号前面确定的数据中选择一个数据,使得即时均衡数据现在处于可判定区域。 这个决定的数据现在被反馈了。