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1. 发明授权

US08165027B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08165027B2
公开(公告)日：2012-04-24
申请号：US12569796
申请日：2009-09-29
申请人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04J1/16
CPC分类号： H04L43/50
摘要： There is provided a test apparatus for testing at least one device under test, including a packet list storing section that stores a plurality of packet lists each of which includes a series of packets communicated between the test apparatus and the at least one device under test, a flow control section that designates an order of executing the plurality of packet lists in accordance with an execution flow of a test program that is designed to test the at least one device under test, and a packet communicating section that sequentially communicates the series of packets included in packet lists sequentially designated by the flow control section between the test apparatus and the at least one device under test, to test the at least one device under test.
摘要翻译：提供了一种用于测试至少一个被测设备的测试装置，包括存储多个分组列表的分组列表存储部分，每个分组列表包括在测试设备和被测试的至少一个设备之间传送的一系列分组，根据被设计为测试被测试的至少一个设备的测试程序的执行流程来指定执行多个分组列表的顺序的流程控制部分，以及顺序地传送一系列分组的分组通信部分包括在由测试装置和被测试的至少一个设备之间由流量控制部分顺序指定的分组列表中，以测试被测试的至少一个设备。

2. 发明授权

US08149721B2 Test apparatus and test method 有权
标题翻译：试验装置及试验方法
公开(公告)号：US08149721B2
公开(公告)日：2012-04-03
申请号：US12569776
申请日：2009-09-29
申请人： Shinichi Ishikawa , Hajime Sugimura , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Hajime Sugimura , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04J1/16
CPC分类号： H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.
摘要翻译：提供了一种用于测试被测设备的测试装置，包括：获取部分，用于从用于模拟被测设备的操作的仿真环境中获取在测试设备和被测设备之间传送的分组序列;分组通信程序生成部，其从所述分组序列生成用于测试的分组通信程序，其中，所述分组通信程序将由所述测试装置执行以将所述分组序列中包括的分组传送到所述测试装置和所述被测试设备之间;以及测试部分执行分组通信程序以通过在测试设备和被测设备之间传送分组来测试待测设备。

3. 发明授权

US07015685B2 Semiconductor tester 失效
标题翻译：半导体测试仪
公开(公告)号：US07015685B2
公开(公告)日：2006-03-21
申请号：US10850050
申请日：2004-05-20
申请人： Hiroyasu Nakayama
发明人： Hiroyasu Nakayama
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R31/31922
摘要： A semiconductor tester for testing a semiconductor device by generating pulses of different repetition periods to a DUT having ports of different periods (frequencies) without using plural timing memories holding timing sets. The semiconductor tester required to generate a timing edge pulse of a period M different from a test period N of the semiconductor tester comprises period converting means capable of generating a timing edge pulse of the period M different from the period N of the test rate without using timing set that the semiconductor tester has.
摘要翻译：一种半导体测试器，用于通过以不同周期（频率）的端口产生具有不同重复周期的脉冲的半导体器件，而不使用保持定时组的多个定时存储器。产生与半导体测试器的测试周期N不同的周期M的定时边沿脉冲所需的半导体测试器包括能够产生不同于测试速率的周期N的周期M的定时边缘脉冲的周期转换装置，而不使用半导体测试仪具有的定时设置。

4. 发明授权

US08666691B2 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US08666691B2
公开(公告)日：2014-03-04
申请号：US13118470
申请日：2011-05-30
申请人： Shinichi Ishikawa , Tetsu Katagiri , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Tetsu Katagiri , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： G06F19/00 , G01R31/28
CPC分类号： G01R31/31711 , G01R31/2834 , G01R31/318511 , G01R31/31935 , H04L41/069 , H04L43/50
摘要： Provided is a test apparatus that tests a device under test, comprising a testing section that stores a program in which commands to be executed branch according to detected branching conditions and that tests the device under test by executing the program; and a log memory that stores test results of the testing section in association with command paths of the program executed to obtain the test results. The testing section sequentially changes a characteristic of a test signal supplied to the device under test, and judges pass/fail of the device under test for each characteristic of the test signal, and the log memory stores a test result of the testing section in association with a command path of the program, for each characteristic of the test signal.
摘要翻译：提供了一种测试被测设备的测试装置，包括：测试部，其存储根据检测到的分支条件进行分支的执行命令的程序，并通过执行程序来测试被测设备; 以及日志存储器，其存储与执行的程序的命令路径相关联的测试部分的测试结果以获得测试结果。测试部分顺序地改变提供给被测设备的测试信号的特性，并且根据测试信号的每个特性判断被测设备的通过/失败，并且日志存储器将测试部分的测试结果相关联具有程序的命令路径，用于测试信号的每个特性。

5. 发明申请

US20110137606A1 TEST APPARATUS AND TEST METHOD 失效
标题翻译：测试装置和测试方法
公开(公告)号：US20110137606A1
公开(公告)日：2011-06-09
申请号：US12962569
申请日：2010-12-07
申请人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu NAKAYAMA , Masaru TSUTO
发明人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu NAKAYAMA , Masaru TSUTO
IPC分类号： G06F19/00
CPC分类号： H04L43/50 , G01R31/2834
摘要： Provided is a test apparatus that tests a device under test, comprising: a plurality of channels that output and receive signals to and from the device under test; a generating section that generates a packet data sequence transmitted to and from the device under test; and a channel selecting section that selects which of the channels is used to transmit the packet data sequence generated by the generating section.
摘要翻译：提供了一种测试被测设备的测试设备，包括：向被测设备输出信号和从被测设备接收信号的多个通道; 生成部，其生成从被测设备发送的分组数据序列; 以及频道选择部，选择哪个信道用于发送由生成部生成的分组数据序列。

6. 发明申请

US20100142393A1 TEST APPARATUS AND TEST METHOD 失效
标题翻译：测试装置和测试方法
公开(公告)号：US20100142393A1
公开(公告)日：2010-06-10
申请号：US12569806
申请日：2009-09-29
申请人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi ISHIKAWA , Masaru GOISHI , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： H04L12/26
CPC分类号： H04L49/90 , H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试设备，包括接收来自被测设备的分组的接收部分，分组数据序列存储部分，其存储包括在每种类型的分组中的数据序列和接收的数据由接收部分接收的分组，发送数据处理部分，其从分组数据序列存储部分读取数据，并通过调整要发送到被测设备的数据包的数据序列的预定部分来生成测试数据序列，以具有与接收到的数据相对应的值，以及发送部，其将由发送数据处理部生成的测试数据序列发送给被测设备。

7. 发明申请

US20060195722A1 Pattern generator and testing apparatus 审中-公开
标题翻译：图案发生器和测试仪器
公开(公告)号：US20060195722A1
公开(公告)日：2006-08-31
申请号：US11336420
申请日：2006-01-20
申请人： Hiroyasu Nakayama
发明人： Hiroyasu Nakayama
IPC分类号： G06F11/00
CPC分类号： G01R31/318547
摘要： There is provided a pattern generator that generates a test pattern for performing a scan test for an electronic device. The pattern generator includes: a main memory that stores a scan pattern data block including pattern data for performing the scan test and a scan sequence data block including an instruction indicative of a sequence by which data in the scan pattern data block should be supplied to the electronic device, in association with each other; and a data expanding section that executes the instruction in the scan sequence data block to expand the pattern data in the corresponding scan pattern data block and generate the test pattern.
摘要翻译：提供了一种模式生成器，其生成用于执行电子设备的扫描测试的测试图案。图案生成器包括：主存储器，其存储包括用于执行扫描测试的图案数据的扫描图案数据块;以及扫描序列数据块，其包括指示扫描图案数据块中的数据应被提供给电子设备，相互联系; 以及数据扩展部分，执行扫描序列数据块中的指令以扩展对应的扫描图形数据块中的图案数据，并生成测试图案。

8. 发明授权

US5903745A Timing generator for plural reference clocks 失效
标题翻译：多个参考时钟的定时发生器
公开(公告)号：US5903745A
公开(公告)日：1999-05-11
申请号：US620102
申请日：1996-03-21
申请人： Hiroyasu Nakayama , Masayuki Itoh
发明人： Hiroyasu Nakayama , Masayuki Itoh
IPC分类号： G01R31/3183 , G01R31/319 , G06F11/22 , G06F1/04
CPC分类号： G01R31/31922
摘要： A timing generator compensates the difference between the reference clock frequencies by converting the base number for generating the timing signals corresponding to the ratio of reference clock frequencies. The timing generator includes: a data memory for dynamically receiving the timing data through the software process to determine the time length of the timing signals where the timing data is formed of a quotient produced by a division of the time length by a time period of a reference clock and a fraction which is a remainder of said division; a counter for counting the number of pulses of a reference clock signal and generating an output signal when the number of counts of the pulse coincides with the quotient; an accumulator for accumulating the fraction data with the fraction data of previous cycle of the reference clock signal and generating a carry signal when the accumulated value exceeds the time period of the reference clock signal; a number converter which converts the timing data provided through the software process based on a first reference clock period Tn by a ratio of the first reference clock period Tn and a second clock period Tm; and means for providing a complementary number -Tm of the second reference clock period Tm to the accumulator.
摘要翻译：定时发生器通过转换用于产生与参考时钟频率的比率相对应的定时信号的基数来补偿参考时钟频率之间的差异。定时发生器包括：数据存储器，用于通过软件处理动态地接收定时数据，以确定定时信号的时间长度，其中定时数据由通过将时间长度除以时间周期产生的商参考时钟和作为所述分割的剩余部分的分数; 用于计数参考时钟信号的脉冲数的计数器，并且当脉冲的计数与商相重合时产生输出信号; 累加器，用于利用参考时钟信号的前一周期的分数数据累加分数数据，并且当累加值超过参考时钟信号的时间周期时产生进位信号; 数字转换器，其通过第一参考时钟周期Tn和第二时钟周期Tm的比率，基于第一参考时钟周期Tn将通过软件处理提供的定时数据转换; 以及用于向累加器提供第二参考时钟周期Tm的互补数量-Tm的装置。

9. 发明授权

US08483073B2 Test apparatus and test method 失效
标题翻译：试验装置及试验方法
公开(公告)号：US08483073B2
公开(公告)日：2013-07-09
申请号：US12569806
申请日：2009-09-29
申请人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Shinichi Ishikawa , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： G01R31/08
CPC分类号： H04L49/90 , H04L41/145 , H04L43/50
摘要： There is provided a test apparatus for testing a device under test, including a receiving section that receives a packet from the device under test, a packet data sequence storing section that stores a data sequence included in each type of packet and received data included in the packet received by the receiving section, a transmission data processing section that reads data from the packet data sequence storing section and generates a test data sequence by adjusting a predetermined portion of a data sequence of a packet to be transmitted to the device under test to have a value corresponding to the received data, and a transmitting section that transmits the test data sequence generated by the transmission data processing section to the device under test.
摘要翻译：提供了一种用于测试被测设备的测试设备，包括接收来自被测设备的分组的接收部分，分组数据序列存储部分，其存储包括在每种类型的分组中的数据序列和接收的数据由接收部分接收的分组，发送数据处理部分，其从分组数据序列存储部分读取数据，并通过调整要发送到被测设备的数据包的数据序列的预定部分来生成测试数据序列，以具有与接收到的数据相对应的值，以及发送部，其将由发送数据处理部生成的测试数据序列发送给被测设备。

10. 发明授权

US08362791B2 Test apparatus additional module and test method 有权
标题翻译：测试仪附加模块和测试方法
公开(公告)号：US08362791B2
公开(公告)日：2013-01-29
申请号：US12557468
申请日：2009-09-10
申请人： Motoo Ueda , Satoshi Iwamoto , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
发明人： Motoo Ueda , Satoshi Iwamoto , Masaru Goishi , Hiroyasu Nakayama , Masaru Tsuto
IPC分类号： G01R31/28 , G01R31/00
CPC分类号： G01R31/31907 , G01R31/31905
摘要： A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test, the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.
摘要翻译：测试装置包括：与被测设备通信的测试模块，以测试被测设备; 连接在被测设备和测试模块之间的附加模块，每个附加模块与被测设备进行通信，所述通信是以较高速度执行的通信和以较低延迟执行的通信中的至少一个，相比之下与测试模块进行通信; 测试头具有分别连接测试模块和附加模块的多个连接器，测试模块和附加模块安装在测试头上; 放置在测试头上的性能板，其连接在多个连接器的至少一部分端子和被测设备之间。测试模块通过性能板连接到附加模块。

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