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1. 发明授权

US5717895A Associative scalar data cache with write-through capabilities for a vector processor 失效
标题翻译：关联标量数据缓存，具有向量处理器的直写功能
公开(公告)号：US5717895A
公开(公告)日：1998-02-10
申请号：US348056
申请日：1994-12-01
申请人： George W. Leedom , William T. Moore
发明人： George W. Leedom , William T. Moore
IPC分类号： G06F12/08
CPC分类号： G06F9/3013 , G06F12/0875 , G06F12/0888 , G06F9/30109 , G06F9/30138 , G06F9/3824
摘要： Method and apparatus for a scalar data cache in a scalar/vector supercomputer. The scalar data cache comprises a cache array and a cache controller. The cache array comprises a plurality of cache frames; each cache frame comprises a plurality of cache lines; and each cache line comprises a plurality of data words. The cache controller performs a broadside compare of the reference address against all addresses held in the cache, and translates the reference address into a cache-array address. For each cache line, there is a corresponding cache-line validity indication which is set "valid" only when every data word in the cache line contains valid data. A cache-line validity comparator operates to provide a cache-line-hit indication if a data word requested is in a valid cache line. A cache-load controller is described for loading data from a common memory into every data word of a cache line and for marking the cache line "valid". For at least one of the plurality of scalar registers, a cache accessor is described for providing fetch access to the data words in the cache array, and for providing write-through-cache capability to the data words in the cache array.
摘要翻译：标量/向量超级计算机中的标量数据缓存的方法和装置。标量数据高速缓存包括高速缓存阵列和高速缓存控制器。高速缓存阵列包括多个缓存帧; 每个缓存帧包括多个高速缓存行; 并且每个高速缓存行包括多个数据字。高速缓存控制器执行参考地址与保存在高速缓存中的所有地址的宽边比较，并将参考地址转换为高速缓存阵列地址。对于每个高速缓存行，只有当高速缓存行中的每个数据字都包含有效数据时，才有一个对应的高速缓存线有效性指示被设置为“有效”。如果请求的数据字在有效的高速缓存行中，则高速缓存行有效性比较器用于提供高速缓存行命中指示。描述了缓存负载控制器，用于将数据从公共存储器加载到高速缓存行的每个数据字中，并用于标记高速缓存行“有效”。对于多个标量寄存器中的至少一个，描述了高速缓存存取器，用于提供对高速缓存阵列中的数据字的取出访问，以及用于向缓存阵列中的数据字提供直写缓存能力。

2. 发明授权

US5390300A Real time I/O operation in a vector processing computer system by running designated processors in privileged mode and bypass the operating system 失效
标题翻译：通过在特权模式下运行指定的处理器并绕过操作系统，在矢量处理计算机系统中实时I / O操作
公开(公告)号：US5390300A
公开(公告)日：1995-02-14
申请号：US200921
申请日：1994-02-22
申请人： Richard D. Pribnow , Galen Flunker , George W. Leedom , Alan J. Schiffleger
发明人： Richard D. Pribnow , Galen Flunker , George W. Leedom , Alan J. Schiffleger
IPC分类号： G06F9/48 , G06F15/17 , G06F9/46 , G06F9/00
CPC分类号： G06F9/4818 , G06F15/17
摘要： The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.
摘要翻译：本发明提供一种适用于实时I / O的向量处理计算机系统。本发明结合了旋转优先级中断方案，用于每个处理器的专用实时中断线路，以及访问实时操作的处理器的特权通信/控制模式，以创建适用于许多不同实际情况的灵活硬件设计时间申请。

3. 发明授权

US6012135A Computer having multiple address ports, each having logical address translation with base and limit memory management 失效
标题翻译：具有多个地址端口的计算机，每个地址端口具有基本的逻辑地址转换和限制存储器管理
公开(公告)号：US6012135A
公开(公告)日：2000-01-04
申请号：US347964
申请日：1994-12-01
申请人： George W Leedom , William T. Moore
发明人： George W Leedom , William T. Moore
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0292
摘要： Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address. A translation controller is connected to the segment detector and the address translator, wherein the translation controller operates to output the physical address if the segment detector determines that the logical address is within the specified address boundaries of the logical segment. One embodiment of the segment-register set includes a base address, a limit address, and a physical mapping bias. One embodiment of the computer includes a plurality of address ports, wherein each address port includes a logical address translator.
摘要翻译：逻辑地址转换器的方法和装置，其将逻辑地址转换成计算机中的物理地址。计算机包括多个地址端口。每个地址端口包括逻辑地址转换器，其包括多个段寄存器集合。每个段寄存器组保存指定相应逻辑段的地址边界和转换映射的值。段检测器耦合到多个段寄存器集合，其中段检测器操作以确定逻辑地址是否在逻辑段的指定地址边界内。地址映射器耦合到多个段寄存器集合，其中地址映射器操作以将逻辑地址转换为物理地址。翻译控制器连接到段检测器和地址转换器，其中如果段检测器确定逻辑地址在逻辑段的指定地址边界内，则翻译控制器操作以输出物理地址。段寄存器集合的一个实施例包括基地址，限制地址和物理映射偏置。计算机的一个实施例包括多个地址端口，其中每个地址端口包括逻辑地址转换器。

4. 发明授权

US5623685A Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency 失效
标题翻译：向量寄存器有效性指示，用于处理具有可变内存延迟的向量计算机的无序元素到达
公开(公告)号：US5623685A
公开(公告)日：1997-04-22
申请号：US347953
申请日：1994-12-01
申请人： George W. Leedom , William T. Moore
发明人： George W. Leedom , William T. Moore
IPC分类号： G06F17/16 , G06F9/38 , G06F15/78 , G06F12/06
CPC分类号： G06F15/8084 , G06F9/30036 , G06F9/3824 , G06F9/3836
摘要： Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a "chunk") in a vector register is loaded from memory, the entire chunk is marked valid and thus made available for use by subsequent or pending operations. The vector processing apparatus comprises a plurality of vector registers, wherein each vector register holds a plurality of elements. For each of the vector registers, a validity indicator is provided wherein each validity indicator indicates a subset of the elements in the corresponding vector register which are valid. A chunk-validation controller is coupled to the validity indicators operable to adjust a value of the validity indicator in response to a plurality of elements becoming valid. An arithmetic logical functional unit (ALFU) is coupled to the vector registers to execute functions specified by program instructions. A vector register controller is connected to control the vector registers in response to program instructions in order to cause valid elements of a selected vector register to be successively transmitted to said ALFU, so that elements are streamed through said ALFU at a speed that is determined by the availability of valid elements from the vector registers. The ALFU optionally comprises a processor pipeline to hold operand data for operations not yet completed while receiving operands for successive operations. The ALFU also optionally comprises an address pipeline to hold element addresses corresponding to the operands for operations not yet completed while receiving element addresses corresponding to the operands for successive operations.
摘要翻译：用于在计算机系统上进行向量处理的方法和装置。由于向量寄存器中的一组元素（称为“块”）的最后一个元素从存储器加载，所以整个块被标记为有效，因此可以被后续或待处理的操作使用。矢量处理装置包括多个向量寄存器，其中每个向量寄存器保持多个元素。对于每个向量寄存器，提供有效性指示符，其中每个有效性指示符指示相应向量寄存器中有效的元素的子集。块验证控制器耦合到有效性指示符，可操作以响应于多个元素变得有效来调整有效性指示符的值。算术逻辑功能单元（ALFU）耦合到矢量寄存器以执行由程序指令指定的功能。连接矢量寄存器控制器以响应于程序指令来控制向量寄存器，以便使所选择的向量寄存器的有效元素被连续发送到所述ALFU，使得元素以所述ALFU的速度被流式化，速度由矢量寄存器中有效元素的可用性。 ALFU可选地包括一个处理器流水线，用于保存操作数据，以便操作尚未完成，同时接收连续操作的操作数。 ALFU还可选地包括地址流水线，用于保存对应于尚未完成的操作的操作数的元件地址，同时接收与用于连续操作的操作数相对应的元件地址。

5. 发明授权

US5247637A Method and apparatus for sharing memory in a multiprocessor system 失效
标题翻译：用于在多处理器系统中共享存储器的方法和装置
公开(公告)号：US5247637A
公开(公告)日：1993-09-21
申请号：US531861
申请日：1990-06-01
申请人： George W. Leedom , Alan J. Schiffleger , Ram K. Gupta
发明人： George W. Leedom , Alan J. Schiffleger , Ram K. Gupta
IPC分类号： G06F15/173
CPC分类号： G06F15/173
摘要： The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.
摘要翻译：本发明提供了一种存储器接口系统，其中提供了具有多个端口并被划分为多个部分的存储器，每个部分被划分成子部分，每个子部分内的存储体，并且划分成至少两个组组的存储体。本发明还提供了一种存储器接口，用于根据它们所在的银行组来控制所述存储器组的参考。

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