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1. 发明申请

US20060114731A1 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US20060114731A1
公开(公告)日：2006-06-01
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

2. 发明授权

US6002629A Integrated circuit memory devices having improved refresh mode addressing and methods of operating same 有权
标题翻译：具有改进的刷新模式寻址的集成电路存储器件及其操作方法
公开(公告)号：US6002629A
公开(公告)日：1999-12-14
申请号：US206683
申请日：1998-12-07
申请人： Jeon-Kyu Kim , Chang-Hag Oh , Choong-Sun Park , Jeon-Hyoung Lee
发明人： Jeon-Kyu Kim , Chang-Hag Oh , Choong-Sun Park , Jeon-Hyoung Lee
IPC分类号： G11C11/403 , G11C11/406 , G11C11/408 , G11C7/00
CPC分类号： G11C11/4087 , G11C11/406
摘要： Integrated circuit memory devices include an array of memory cells and a row address generator circuit which generates first and second different sequences of addresses during first and second refresh modes, respectively, and also repeats at least one of the addresses in the first sequence as an address in the second sequence when transitioning from the first refresh mode to the second refresh mode. The generator circuit may also perform the function of generating row addresses during the first and second refresh modes with the most significant bit of a row address being toggled with each consecutive row address during the first refresh mode. The first refresh mode may be a CAS-before-RAS refresh mode, the second refresh mode may be a self-refresh mode and the address in at least one of the first and second periods of the self-refresh mode may be equivalent to an address in the last period of a preceding CAS-before-RAS refresh mode when transitioning from the first refresh mode to the second refresh mode. This repetition in addressing prevents one or more row of memory cells from being skipped when transitioning from one refresh mode to another refresh mode.
摘要翻译：集成电路存储器件包括存储器单元阵列和行地址发生器电路，其分别在第一和第二刷新模式期间产生第一和第二不同的地址序列，并且还将第一序列中的至少一个地址重复为地址在从第一刷新模式转换到第二刷新模式的第二序列中。发生器电路还可以执行在第一和第二刷新模式期间产生行地址的功能，其中在第一刷新模式期间行地址的最高有效位与每个连续行地址切换。第一刷新模式可以是CAS-before-RAS刷新模式，第二刷新模式可以是自刷新模式，并且自刷新模式的第一和第二周期中的至少一个中的地址可以等效于在从第一刷新模式转换到第二刷新模式时，在先前的CAS-before-RAS刷新模式的最后期间中的地址。这种在寻址中的重复防止当从一个刷新模式转换到另一刷新模式时跳过一行或多行存储器单元。

3. 发明授权

US07173872B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07173872B2
公开(公告)日：2007-02-06
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

4. 发明授权

US07016248B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07016248B2
公开(公告)日：2006-03-21
申请号：US10423505
申请日：2003-04-25
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号（例如，晶片烧入测试模式）使得高电压发生器能够使能的使能信号。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

5. 发明授权

US06396754B1 Semiconductor memory device which controls sense amplifier for detecting bit line bridge and method of controlling the semiconductor memory device 失效
公开(公告)号：US06396754B1
公开(公告)日：2002-05-28
申请号：US09901050
申请日：2001-07-10
申请人： Hyong-yong Lee , Suk-bae Jun , Choong-sun Park
发明人： Hyong-yong Lee , Suk-bae Jun , Choong-sun Park
IPC分类号： G11C2900
CPC分类号： G11C29/02
摘要： In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.

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