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1. 发明申请

US20140071590A1 STACKED-TYPE SOLID ELECTROLYTIC CAPACITOR PACKAGE STRUCTURE 有权
标题翻译：堆叠型固体电解电容器封装结构
公开(公告)号：US20140071590A1
公开(公告)日：2014-03-13
申请号：US13613098
申请日：2012-09-13
申请人： Ching-Feng LIN , Chi-Hao CHIU , Kun-Huang CHANG
发明人： Ching-Feng LIN , Chi-Hao CHIU , Kun-Huang CHANG
IPC分类号： H01G9/08 , H01G9/15
CPC分类号： H01G9/012 , H01G9/08 , H01G9/15
摘要： A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit and a conductive unit. The capacitor unit includes a plurality of capacitors stacked on top of one another. The package unit includes a package body enclosing the capacitors. The package body has a top surface defining a package length, a package width and an effective package, and the package width is substantially between 85% and 95% of the package length. The conductive unit includes a first conductive terminal electrically connected to the positive portion of the capacitor and a second conductive terminal electrically connected to the negative portion of the capacitor. One part of the first conductive terminal and one part of the second conductive terminal are enclosed by the package body, and another part of the first conductive terminal and another part of the second conductive terminal are exposed from the package body.
摘要翻译：叠层型固体电解电容器封装结构包括电容器单元，封装单元和导电单元。电容器单元包括堆叠在彼此顶部的多个电容器。封装单元包括封装电容器的封装体。包装体具有限定包装长度，包装宽度和有效包装的顶表面，并且包装宽度基本上在包装长度的85％至95％之间。导电单元包括电连接到电容器的正部分的第一导电端子和电连接到电容器的负极部分的第二导电端子。第一导电端子的一部分和第二导电端子的一部分被封装体包围，并且第一导电端子的另一部分和第二导电端子的另一部分从封装体露出。

2. 发明授权

US08390991B2 Stacked solid-state electrolytic capacitor with multi-directional product lead frame structure 有权
标题翻译：堆叠式固态电解电容器具有多方向产品引线框架结构
公开(公告)号：US08390991B2
公开(公告)日：2013-03-05
申请号：US12833421
申请日：2010-07-09
申请人： Chi-Hao Chiu , Yui-Shin Fran , Ching-Feng Lin , Chun-Chia Huang , Chun-Hung Lin , Wen-Yen Huang
发明人： Chi-Hao Chiu , Yui-Shin Fran , Ching-Feng Lin , Chun-Chia Huang , Chun-Hung Lin , Wen-Yen Huang
IPC分类号： H01G9/04 , H01G9/15 , H01G4/228
CPC分类号： H01G9/00
摘要： A stacked solid state solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. The substrate unit includes a positive guiding substrate and a negative guiding substrate. The positive guiding substrate has a positive exposed end integrally extended therefrom along a first predetermined direction. The negative guiding substrate has a first negative exposed end integrally extended therefrom along a second predetermined direction, a second negative exposed end integrally extended therefrom along a third predetermined direction, and a third negative exposed end integrally extended therefrom along a fourth predetermined direction. The first, the second, the third and the fourth predetermined directions are different. The capacitor units are stacked on top of one another and disposed on the negative guiding substrate. The package unit encloses the capacitor units, one part of the positive and one part of the negative guiding substrate.
摘要翻译：堆叠的固态固体电解电容器包括多个电容器单元，基板单元和封装单元。基板单元包括正引导基板和负引导基板。正引导基板具有沿着第一预定方向从其一体延伸的正露出端。负引导基板具有沿着第二预定方向从其一体地延伸的第一负外露端，沿着第三预定方向从其一体地延伸的第二负外露端，以及沿着第四预定方向从其一体地延伸的第三负外露端。第一，第二，第三和第四预定方向是不同的。电容器单元堆叠在彼此的顶部并且设置在负引导基板上。封装单元包围电容器单元，正极的一部分和负引导基板的一部分。

3. 发明授权

US08305735B2 Stacked solid electrolytic capacitor with multi-pin structure 有权
标题翻译：堆叠固体电解电容器，多引脚结构
公开(公告)号：US08305735B2
公开(公告)日：2012-11-06
申请号：US12627576
申请日：2009-11-30
申请人： Yui-Shin Fran , Ching-Feng Lin , Chi-Hao Chiu , Chun-Chia Huang , Wen-Yen Huang
发明人： Yui-Shin Fran , Ching-Feng Lin , Chi-Hao Chiu , Chun-Chia Huang , Wen-Yen Huang
IPC分类号： H01G4/228 , H01G5/38 , H01G9/00
CPC分类号： H01G9/15 , H01G2/06 , H01G9/012 , Y02T10/7022
摘要： A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：具有正多引脚结构的堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元的正电极具有从其向外延伸的正极销。正极引脚分为多个彼此分离并彼此电叠置的正极引脚单元。每个电容器单元的负极具有从其向外延伸的负极销。负引脚分为多个负引脚单元。负引脚单元彼此分离，并且每个负引脚单元的负引脚彼此电叠置。基板单元具有与正极引脚电连接的正引导基板和与负引脚电连接的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

4. 发明申请

US20120092810A1 INSULATING ENCAPSULATION STRUCTURE FOR SOLID CHIP ELECTROLYTIC CAPACITOR 有权
标题翻译：固体芯片电解电容器的绝缘封装结构
公开(公告)号：US20120092810A1
公开(公告)日：2012-04-19
申请号：US12907158
申请日：2010-10-19
申请人： CHI-HAO CHIU , MING-TSUNG CHEN , CHIAO-YINMS YANG
发明人： CHI-HAO CHIU , MING-TSUNG CHEN , CHIAO-YINMS YANG
IPC分类号： H01G9/08
CPC分类号： H01G9/15 , H01G9/08
摘要： An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced.
摘要翻译：绝缘封装结构被应用于包括具有铝芯层的铝金属体的芯片型固体电解电容器。在铝芯层的顶部和底部分别形成表面上分别具有细孔的上氧化膜和低氧化膜。金属体的侧面是多个切割毛刺。金属体的上部氧化物膜和下部氧化物膜分别通过分离层分离以形成阳极和阴极。绝缘封装结构包括封闭金属体的外表面以覆盖切割毛刺的绝缘覆盖层。因此，随着电流泄漏，所需的化学转化过程减少，整体制造成本降低，并且增强了金属体边缘的机械强度。

5. 发明申请

US20110007451A1 STACKED SOLID ELECTROLYTIC CAPACITOR WITH MULTI-PIN STRUCTURE 有权
标题翻译：具有多引脚结构的堆叠固体电解电容器
公开(公告)号：US20110007451A1
公开(公告)日：2011-01-13
申请号：US12627576
申请日：2009-11-30
申请人： Yui-Shin Fran , Ching-Feng Lin , Chi-Hao Chiu , Chun-Chia Huang , Wen-Yen Huang
发明人： Yui-Shin Fran , Ching-Feng Lin , Chi-Hao Chiu , Chun-Chia Huang , Wen-Yen Huang
IPC分类号： H01G9/00
CPC分类号： H01G9/15 , H01G2/06 , H01G9/012 , Y02T10/7022
摘要： A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：具有正多引脚结构的堆叠固体电解电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元的正电极具有从其向外延伸的正极销。正极引脚分为多个彼此分离并彼此电叠置的正极引脚单元。每个电容器单元的负极具有从其向外延伸的负极销。负引脚分为多个负引脚单元。负引脚单元彼此分离，并且每个负引脚单元的负引脚彼此电叠置。基板单元具有与正极引脚电连接的正引导基板和与负引脚电连接的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

6. 发明申请

US20110002087A1 Stacked capacitor with positive multi-pin structure 有权
标题翻译：具有正多引脚结构的堆叠电容器
公开(公告)号：US20110002087A1
公开(公告)日：2011-01-06
申请号：US12588186
申请日：2009-10-07
申请人： Chi-Hao Chiu , Yui-Hsin Fran , Ching-Feng Lin , Chun-Chia Huang
发明人： Chi-Hao Chiu , Yui-Hsin Fran , Ching-Feng Lin , Chun-Chia Huang
IPC分类号： H01G9/00
CPC分类号： H01G9/26 , H01G9/008 , H01G9/08
摘要： A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
摘要翻译：具有正多引脚结构的堆叠电容器包括多个电容器单元，基板单元和封装单元。每个电容器单元具有正极，其具有从其向外延伸的正极销。电容器单元的正极引脚被分成多个彼此分离的正极引脚单元，并且每个正极引脚单元的正极引脚彼此电叠置。每个电容器单元具有负电极，并且电容器单元的负电极彼此电叠置。基板单元具有电连接到电容器单元的正极的正引导基板和电连接到电容器单元的负极的负引导基板。封装单元覆盖电容器单元和衬底单元的一部分。

7. 发明申请

US20070085218A1 FLIP CHIP PACKAGE 审中-公开
标题翻译： FLIP芯片包
公开(公告)号：US20070085218A1
公开(公告)日：2007-04-19
申请号：US11563029
申请日：2006-11-24
申请人： Yu-Wen Chen , Chih-Ming Chung , Chi-Hao Chiu
发明人： Yu-Wen Chen , Chih-Ming Chung , Chi-Hao Chiu
IPC分类号： H01L23/48
CPC分类号： H01L24/28 , H01L21/563 , H01L23/36 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/73203 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2224/05599
摘要： A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
摘要翻译：提供了一种倒装芯片封装结构。芯片电连接到基板。散热片连接到芯片的背面。散热器至少具有位于周边区域并且横向邻近芯片的通孔。进行分配处理以通过通孔输送底部填充材料，使得填充芯片和基板之间的空间。底部填充材料还延伸以覆盖散热器的一部分，使得散热器和基板连接在一起。固化底部填充材料以将散热器，基板和芯片固定就位。

8. 发明授权

US07164202B2 Quad flat flip chip package and leadframe thereof 有权
标题翻译：四平面倒装芯片封装及其引线框架
公开(公告)号：US07164202B2
公开(公告)日：2007-01-16
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/48
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

9. 发明申请

US20050156296A1 QUAD FLAT FLIP CHIP PACKAGE AND LEADFRAME THEREOF 有权
标题翻译：四边形平板纸芯片包装和铅笔
公开(公告)号：US20050156296A1
公开(公告)日：2005-07-21
申请号：US10904517
申请日：2004-11-15
申请人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
发明人： Hsueh-Te Wang , Meng-Jen Wang , Chien Liu , Chi-Hao Chiu
IPC分类号： H01L23/31 , H01L23/433 , H01L23/495
CPC分类号： H01L23/49551 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01322 , H01L2924/18161 , H01L2224/05599
摘要： A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
摘要翻译：提供了四平面倒装芯片封装及其引线框。通过弯曲或蚀刻引线框架的引线来限定凸块连接部分。因此，在回流焊接工序之后形成的凸点被限制在凸块连接部内，并且可以防止凸块的塌陷。此外，可以减少包装的制造成本，并且可以简化其处理。

10. 发明申请

US20130010404A1 CAPACITANCE UNIT AND STACKED SOLID ELECTROLYTIC CAPACITOR 有权
标题翻译：电容单元和堆叠固体电解电容器
公开(公告)号：US20130010404A1
公开(公告)日：2013-01-10
申请号：US13178464
申请日：2011-07-07
申请人： CHI-HAO CHIU , CHING-FENG LIN , KUN-HUANG CHANG
发明人： CHI-HAO CHIU , CHING-FENG LIN , KUN-HUANG CHANG
IPC分类号： H01G9/15 , H01G9/028 , H01G9/00
CPC分类号： H01G9/012 , H01G9/10 , H01G9/14 , H01G9/15
摘要： A capacitance unit includes an anode portion, an insulating portion, a cathode portion and a colloid portion. The front end of the anode portion extends to from an anode terminal. The insulating portion surrounds the anode portion and covers a first partial surface of the anode portion. The cathode portion is disposed next to the insulating portion, and the cathode portion covers a second partial surface of the anode portion. The colloid portion is disposed next to the insulating portion, and the colloid portion surrounds the cathode portion and covers a partial surface of the cathode portion.
摘要翻译：电容单元包括阳极部分，绝缘部分，阴极部分和胶体部分。阳极部分的前端从阳极端子延伸。绝缘部分包围阳极部分并且覆盖阳极部分的第一部分表面。阴极部分靠近绝缘部分设置，阴极部分覆盖阳极部分的第二部分表面。胶体部分靠近绝缘部分设置，胶体部分包围阴极部分并覆盖阴极部分的部分表面。

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