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1. 发明申请

US20080107165A1 Method and apparatus for layer 1 / layer 2 convergence declaration for an adaptive equalizer 有权
标题翻译：自适应均衡器的层1 /层2收敛声明的方法和装置
公开(公告)号：US20080107165A1
公开(公告)日：2008-05-08
申请号：US11593652
申请日：2006-11-07
申请人： Alex Nicolescu , Kenji Suzuki , Brian Wall , Michael McDonnell
发明人： Alex Nicolescu , Kenji Suzuki , Brian Wall , Michael McDonnell
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04J3/0602 , H04J2203/006 , H04J2203/0089 , H04L2025/037
摘要： A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 10G-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.
摘要翻译：公开了一种新颖的方法和装置，其嵌入或适用于适用于IEEE 10G-LRM标准兼容接收器的自适应均衡器，数字逻辑监视第1层中的一些，并且优选地监视第2层处理中的一些这通常在解码和处理记录数据流之后的均衡步骤之后发生。根据该附加逻辑信息，均衡器能够通过对处理误差进行计数并通过计算BER来证明收敛，从而对均衡器收敛进行更准确的预测。新颖的方法和装置适用于ASIC实施例，并且根据特定通信环境，所获得的逻辑信息的复杂性可以根据特定的可编程地缩减或增强。

2. 发明授权

US08184686B2 System and method for recovering data received over a communication channel 有权
标题翻译：用于恢复通过通信信道接收的数据的系统和方法
公开(公告)号：US08184686B2
公开(公告)日：2012-05-22
申请号：US11651632
申请日：2007-01-10
申请人： Brian Wall , Stephane Dallaire , Stephen Alie , Kenji Suzuki
发明人： Brian Wall , Stephane Dallaire , Stephen Alie , Kenji Suzuki
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H03L7/08 , H04L7/0087 , H04L7/033 , H04L2025/03503
摘要： According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.
摘要翻译：根据第一方面，提供一种用于恢复通过通信信道接收的数据的电路。该电路包括可操作以从接收信号中去除ISI（符号间干扰）的自适应均衡器和可操作以对恢复数据进行采样的定时恢复电路。定时恢复电路包括基于霍格相位检测器的检测器。根据另一方面，提供了一种可以实现电路的模块。根据另一方面，提供了一种用于恢复在通信信道上接收的数据的方法。该方法包括使用自适应均衡器从接收到的信号中去除ISI，并且使用基于霍格相位检测器的检测器对恢复的数据进行采样。根据另一方面，定时恢复电路包括多个相位检测器，每个相位检测器可操作以对恢复的数据进行采样。提供选择器用于选择要输出哪些采样的恢复数据。

3. 发明授权

US07912161B2 Method and apparatus for layer 1 / layer 2 convergence declaration for an adaptive equalizer 有权
标题翻译：自适应均衡器的层1 /层2收敛声明的方法和装置
公开(公告)号：US07912161B2
公开(公告)日：2011-03-22
申请号：US11593652
申请日：2006-11-07
申请人： Alex Nicolescu , Kenji Suzuki , Brian Wall , Michael McDonnell
发明人： Alex Nicolescu , Kenji Suzuki , Brian Wall , Michael McDonnell
IPC分类号： H03D1/06 , H03D11/04 , H03K5/01 , H03K6/04 , H04B1/10 , H04L1/00 , H04L25/08
CPC分类号： H04L25/03057 , H04J3/0602 , H04J2203/006 , H04J2203/0089 , H04L2025/037
摘要： A novel method and apparatus is disclosed, that embeds with, or otherwise makes available to an adaptive equalizer, suitable for use in IEEE 1OG-LRM standard compliant receivers, digital logic that monitors some of the Layer 1 and preferably some of the Layer 2 processing that typically occurs after the equalization step during decoding and processing of the record data stream. From this additional logic information, the equalizer is able to make a much more accurate prediction of equalizer convergence by counting processing errors and prove convergence by calculation of BER. The novel method and apparatus are applicable to ASIC embodiments and the complexity of the logic information obtained can be programmably scaled back or enhanced as appropriate in light of the particular communication environment.
摘要翻译：公开了一种新颖的方法和装置，其嵌入或以其他方式可用于自适应均衡器，适用于IEEE 1OG-LRM标准兼容接收器，数字逻辑，其监视第1层中的一些，优选地监视第2层处理中的一些这通常在解码和处理记录数据流之后的均衡步骤之后发生。根据该附加逻辑信息，均衡器能够通过对处理误差进行计数并通过计算BER来证明收敛，从而对均衡器收敛进行更准确的预测。新颖的方法和装置适用于ASIC实施例，并且根据特定通信环境，所获得的逻辑信息的复杂性可以根据特定的可编程地缩减或增强。

4. 发明授权

US07519750B2 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US07519750B2
公开(公告)日：2009-04-14
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F13/00 , G06F13/42 , G06F12/00 , H03L7/06 , H03K5/01
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

5. 发明申请

US20080165841A1 System and method for recovering data received over a communication channel 有权
标题翻译：用于恢复通过通信信道接收的数据的系统和方法
公开(公告)号：US20080165841A1
公开(公告)日：2008-07-10
申请号：US11651632
申请日：2007-01-10
申请人： Brian Wall , Stephane Dallaire , Stephen Alie , Kenji Suzuki
发明人： Brian Wall , Stephane Dallaire , Stephen Alie , Kenji Suzuki
IPC分类号： H04L25/08
CPC分类号： H04L25/03057 , H03L7/08 , H04L7/0087 , H04L7/033 , H04L2025/03503
摘要： According to a first aspect, there is provided a circuit for recovering data received over a communication channel. The circuit includes an adaptive equalizer operable to remove ISI (intersymbol interference) from a received signal and a timing recovery circuit operable to sample recovered data. The timing recovery circuit includes a detector based on a Hogge Phase detector. According to another aspect, there is provided a module in which the circuit may be implemented. According to another aspect, there is provided a method for recovering data received over a communication channel. The method involves removing ISI from a received signal using an adaptive equalizer, and sampling recovered data using a detector based on a Hogge phase detector. According to another aspect, the timing recovery circuit includes a plurality of phase detectors, each one being operable to sample recovered data. A selector is provided for selecting which sampled recovered data is to be output.
摘要翻译：根据第一方面，提供一种用于恢复通过通信信道接收的数据的电路。该电路包括可操作以从接收信号中去除ISI（符号间干扰）的自适应均衡器和可操作以对恢复数据进行采样的定时恢复电路。定时恢复电路包括基于霍格相位检测器的检测器。根据另一方面，提供了一种可以实现电路的模块。根据另一方面，提供了一种用于恢复在通信信道上接收的数据的方法。该方法包括使用自适应均衡器从接收到的信号中去除ISI，并且使用基于霍格相位检测器的检测器对恢复的数据进行采样。根据另一方面，定时恢复电路包括多个相位检测器，每个相位检测器可操作以对恢复的数据进行采样。提供选择器用于选择要输出哪些采样的恢复数据。

6. 发明申请

US20080022143A1 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US20080022143A1
公开(公告)日：2008-01-24
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F1/12
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

7. 发明申请

US20090016477A1 Signal timing phase selection and timing acquisition apparatus and techniques 有权
标题翻译：信号定时相位选择和定时采集装置及技术
公开(公告)号：US20090016477A1
公开(公告)日：2009-01-15
申请号：US11822725
申请日：2007-07-09
申请人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
发明人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H03L7/0812 , H03L7/099
摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要翻译：公开了信号定时相位选择和定时获取装置和技术。从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。每个定时相位可以对接收到的信号进行一次或多次采样。在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

8. 发明授权

US07308060B1 Self correcting data re-timing circuit and method 有权
标题翻译：自校正数据重新定时电路及方法
公开(公告)号：US07308060B1
公开(公告)日：2007-12-11
申请号：US10373301
申请日：2003-02-26
申请人： Brian Wall , Shawn Scouten , Kenji Suzuki , Malcolm Stevens
发明人： Brian Wall , Shawn Scouten , Kenji Suzuki , Malcolm Stevens
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/081 , H03L7/18
摘要： An eye opener circuit is provided which performs a data re-timing/eye opening function on a data signal after having been corrupted by jitter. The circuit uses a PLL driven by a clock source which was the same clock source used in timing the data signal originally. The PLL generates a local clock used to re-time the data. A phase error may be introduced into the PLL, or into the data signal.
摘要翻译：提供一种开眼器电路，其在被抖动破坏之后对数据信号执行数据重新定时/眼睛打开功能。该电路使用由时钟源驱动的PLL，该时钟源是与原始数据信号定时相同的时钟源。 PLL产生用于重新定时数据的本地时钟。相位误差可能被引入PLL或数据信号。

9. 发明授权

US07848474B2 Signal timing phase selection and timing acquisition apparatus and techniques 有权
标题翻译：信号定时相位选择和定时采集装置及技术
公开(公告)号：US07848474B2
公开(公告)日：2010-12-07
申请号：US11822725
申请日：2007-07-09
申请人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
发明人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H03L7/0812 , H03L7/099
摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要翻译：公开了信号定时相位选择和定时获取装置和技术。从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。每个定时相位可以对接收到的信号进行一次或多次采样。在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

10. 发明授权

US5441051A Method and apparatus for the non-invasive detection and classification of emboli 失效
标题翻译：用于非侵入性检测和分类栓塞的方法和装置
公开(公告)号：US5441051A
公开(公告)日：1995-08-15
申请号：US386297
申请日：1995-02-09
申请人： Ronald E. Hileman , Brian Wall , David A. Stump
发明人： Ronald E. Hileman , Brian Wall , David A. Stump
IPC分类号： A61B8/06 , G01S7/52 , A61B8/00
CPC分类号： A61B8/06 , G01S7/52036
摘要： A method and apparatus for ultrasonically detecting an embolus in blood flow includes an ultrasound transducer for transmitting ultrasound pulses into the blood flow being interrogated and receiving reflections from acoustic impedance changes in the body. The reflected signals are converted to an electronic signal representation which is subsequently processed to detect and classify emboli in the blood flow. A short duration, broad bandwidth ultrasound signal is used to preserve the polarity of the reflected signal. The polarity is then used to classify the emboli based on a positive or negative reflection coefficient. Emboli having a negative reflection coefficient are classified as either gaseous or fat particles, and emboli having a positive reflection coefficient are classified as solid particles. The emboli can be further classified based on the amplitude of the reflected signal, or designated features of the time waveform or FFT of the reflected signal.
摘要翻译：用于超声波检测血流中血栓的方法和装置包括超声波换能器，用于将超声脉冲发送到被询问的血流中，并接收来自体内声阻抗变化的反射。反射信号被转换成电子信号表示，其随后被处理以检测和分类血液中的栓塞。使用短持续时间的宽带超声信号来保持反射信号的极性。然后使用极性根据正或负反射系数对栓子进行分类。具有负反射系数的Emboli被分类为气体或脂肪颗粒，并且具有正反射系数的栓塞被分类为固体颗粒。可以基于反射信号的幅度或反射信号的时间波形或FFT的指定特征来进一步分类栓塞。

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