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1. 发明授权

US10522651B2 Semiconductor device and manufacturing method therefor 有权
公开(公告)号：US10522651B2
公开(公告)日：2019-12-31
申请号：US15823029
申请日：2017-11-27
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Zhuofan Chen , Haiyang Zhang
IPC分类号： H01L21/338 , H01L29/66 , H01L21/762 , H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/78
摘要： The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.

2. 发明授权

US08816449B2 Self-aligned MOS structure with local interconnects and self-aligned source/drain polysilicon contacts 有权
标题翻译：具有局部互连和自对准源/漏多晶硅触点的自对准MOS结构
公开(公告)号：US08816449B2
公开(公告)日：2014-08-26
申请号：US14029777
申请日：2013-09-17
申请人： Semiconductor Manufacturing International (Shanghai) Coporation
发明人： Tzu-Yin Chiu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/78 , H01L21/28525 , H01L21/76889 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers.
摘要翻译：集成电路结构具有包括阱区域和表面区域的衬底，阱区域内的隔离区域，覆盖在表面区域上的栅极绝缘层，衬底的阱区域内的第一和第二源极/漏极区域。该结构还具有形成在第一和第二源极/漏极区域之间并且在栅极绝缘层附近以及覆盖栅极绝缘层并耦合到沟道区域的栅极层的沟道区域。该结构在栅极层的边缘上具有侧壁间隔物以隔离栅极层，覆盖衬底的表面区域并且具有在第一源极/漏极区域附近延伸的边缘区域的局部互连层。与第一源极/漏极区域上的与边缘区域接触的接触层，并且具有邻接侧壁间隔物的一部分的部分。

3. 发明授权

US09793173B2 Semiconductor device and related manufacturing method 有权
公开(公告)号：US09793173B2
公开(公告)日：2017-10-17
申请号：US15138963
申请日：2016-04-26
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Deyuan Xiao
IPC分类号： H01L27/12 , H01L21/8252 , H01L21/84 , H01L29/66 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/8252 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L29/665 , H01L29/7839
摘要： A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.

4. 发明授权

US08884363B2 System and method for integrated circuits with cylindrical gate structures 有权
标题翻译：具有圆柱形栅极结构的集成电路的系统和方法
公开(公告)号：US08884363B2
公开(公告)日：2014-11-11
申请号：US12892881
申请日：2010-09-28
申请人： De Yuan Xiao , Guo Qing Chen , Roger Lee , Chin Fu Yen , Su Xing , Xiao Lu Huang , Yong Sheng Yang
发明人： De Yuan Xiao , Guo Qing Chen , Roger Lee , Chin Fu Yen , Su Xing , Xiao Lu Huang , Yong Sheng Yang
IPC分类号： H01L29/66 , H01L29/423 , H01L29/06 , B82Y10/00 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/28035 , H01L21/31133 , H01L21/324 , H01L21/84 , H01L29/0665 , H01L29/42376 , H01L29/4238 , H01L29/42392 , H01L29/4916 , H01L29/6656 , H01L29/66795 , H01L29/7854 , H01L29/78696
摘要： A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel.
摘要翻译：公开了一种具有周围栅极结构的集成电路的系统和方法。集成电路系统包括晶体管，其具有围绕圆柱形（GAAC）纳米线通道的栅极，具有插入的介电层。位于半导体布线图案的中间部分的圆柱形纳米线通道连接位于相同导线图案的两个相对端部处的源极和漏极区域。提供了一种用于制造具有包括在SOI晶片的掩埋氧化物层上形成SOI层布线图案的GAAC晶体管的集成电路系统的方法; 在导线图案的中间部分下方形成空腔，并将中间部分成形为圆柱形通道; 用插入的栅极介电层形成围绕所述圆柱形沟道区的栅电极，所述栅电极垂直于所述导线图案位于所述掩埋氧化物层上; 在栅极电极和沟道的任一侧上的导线图案的两个相对端部处形成源极/漏极区域。

5. 发明授权

US08815615B2 Method for copper hillock reduction 有权
标题翻译：铜小丘降低的方法
公开(公告)号：US08815615B2
公开(公告)日：2014-08-26
申请号：US12938158
申请日：2010-11-02
申请人： Duo Hui Bei , Ming Yuan Liu , Chun Sheng Zheng
发明人： Duo Hui Bei , Ming Yuan Liu , Chun Sheng Zheng
IPC分类号： G01R31/26
CPC分类号： H01L21/76877 , H01L21/02167 , H01L21/02299 , H01L21/76883
摘要： A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an intermetal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic.
摘要翻译：在集成电路中形成互连的方法包括提供半导体衬底并形成覆盖在层间电介质层的厚度内的阻挡层的铜互连结构。铜互连结构具有第一应力特性。该方法还将包括铜互连结构的半导体衬底加载到包含惰性环境的沉积室中。包括铜互连结构的半导体衬底在惰性环境中退火一段时间，以使铜互连结构具有第二应力特性。将半导体衬底保持在沉积室中，同时沉积蚀刻停止层。该方法还沉积覆盖在蚀刻停止层上的金属间电介质层，其中退火减少了由至少第一应力特性导致的铜小丘缺陷。

6. 发明授权

US10658239B2 Wafer dicing method 有权
公开(公告)号：US10658239B2
公开(公告)日：2020-05-19
申请号：US16106690
申请日：2018-08-21
申请人： Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Lihui Lu , Chunchao Fei , Po Yuan Chiang , Yaping Wang
IPC分类号： H01L21/301 , H01L21/46 , H01L21/78 , B23K26/40 , B23K26/53 , B23K26/00 , H01L21/683 , H01L21/304 , B23K26/57 , B23K101/40 , B23K103/00
摘要： This disclosure provides wafer dicing methods, and relates to the field of semiconductor technologies. Implementations of the dicing method may include: performing laser stealth dicing processing on a wafer from a back surface of the wafer; performing grinding and thinning processing on the back surface of the wafer after performing the laser stealth dicing processing; sticking a dicing tape on the back surface of the wafer after performing the grinding and thinning processing; and performing separation processing on the wafer after sticking the dicing tape. In some implementations, stealth dicing (SD) is performed before grinding, so that a laser is directly imposed on a back surface of a wafer, thereby alleviating a laser attenuation problem and lowering requirements on light transmittance of a dicing tape.

7. 发明授权

US10236216B2 Method for manufacturing a semiconductor device having a fin located on a substrate 有权
公开(公告)号：US10236216B2
公开(公告)日：2019-03-19
申请号：US15723723
申请日：2017-10-03
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , SMIC Advanced Technology Research & Development (Shanghai) Corporation , IMEC International
发明人： Hai Zhao , Yang Liu , Gang Mao , Cheng-Jui Yang , Yongmeng Lee , Shaofeng Yu
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78 , H01L29/16 , H01L29/165
摘要： The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.

8. 发明授权

US10211738B2 DC-DC conversion circuit system and forming method thereof 有权
公开(公告)号：US10211738B2
公开(公告)日：2019-02-19
申请号：US15976090
申请日：2018-05-10
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Qian Weng
IPC分类号： H02M3/158 , H02M1/15
摘要： The present application relates to the field of circuit design, and discloses a DC-DC conversion circuit system and a forming method thereof. The system may include a primary switch circuit, a charge/discharge circuit, and a secondary switch circuit. The primary switch circuit includes a voltage supply end configured to receive a first direct current voltage and an output end. The charge/discharge circuit includes an input end connected to the output end of the primary switch circuit, and a first output end configured to output a second direct current voltage. The secondary switch circuit includes a voltage supply end configured to receive the first direct current voltage, and an output end connected to the output end of the primary switch circuit. The primary switch circuit is configured to control the charge/discharge circuit to charge or discharge. When a charging current or a discharging current of the charge/discharge circuit is greater than a corresponding threshold, the secondary switch circuit is configured to shunt the charging current or the discharging current. The present application can effectively suppress a ripple of an output voltage, and improve stability of the DC-DC conversion circuit system.

9. 发明授权

US08817435B2 Integrated electrostatic discharge (ESD) device 有权
标题翻译：集成静电放电（ESD）器件
公开(公告)号：US08817435B2
公开(公告)日：2014-08-26
申请号：US13291093
申请日：2011-11-07
申请人： Chi Kang Liu , Ta Lee Yu , Quan Li
发明人： Chi Kang Liu , Ta Lee Yu , Quan Li
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H01L27/088 , H01L29/76
CPC分类号： H01L27/0259 , H01L29/7835
摘要： A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.
摘要翻译：一种制造半导体器件的方法包括提供第一导电类型的衬底，并具有表面区域，形成第二导电类型的阱区域并且在衬底中具有第一深度，添加覆盖在表面区域上的栅极电介质层，添加覆盖所述栅介质层的栅极层，形成所述第一导电类型的第一LDD区，并且在所述阱区内具有第二深度，在所述第一LDD区内形成所述第二导电类型的发射极区，以及形成第二LDD 具有阱区的第一导电类型的区域，沟道区域分离第一和第二LDD区域。该方法还包括在第二LDD区域内形成具有第一导电类型的源极区域，并且将耦合到漏极和发射极区域的输出焊盘相加。

10. 发明授权

US08249737B2 Rapid thermal annealing method for a semiconductor device 有权
标题翻译：半导体器件的快速热退火方法
公开(公告)号：US08249737B2
公开(公告)日：2012-08-21
申请号：US12708469
申请日：2010-02-18
申请人： Jianhua Ju , Xianjie Ning
发明人： Jianhua Ju , Xianjie Ning
IPC分类号： G06F19/00
CPC分类号： H01L27/0207 , H01L21/2686 , H01L21/76224
摘要： The present invention discloses a rapid thermal annealing method for a semiconductor device, which includes the steps of: establishing a ternary correspondence relationship among a device electrical parameter, an annealing temperature, and an STI distribution density; deriving an STI distribution density in a specific area of the semiconductor device and a target STI distribution density; determining whether the STI distribution density in the specific area is larger than the target STI distribution density; if the STI distribution density in the specific area is larger than the target STI distribution density, adding a virtual structure in the specific area to make the STI distribution density in the specific area equal to the target STI distribution density; and deriving from the ternary correspondence relationship a target annealing temperature corresponding to the target STI distribution density and performing an annealing process with the annealing temperature on the semiconductor device to achieve a target electrical parameter. The method can alleviate the phenomenon of temperature non-uniformity of a rapid thermal annealing process so as to avoid any influence thereof upon the electrical performance of the semiconductor device.
摘要翻译：本发明公开了一种半导体器件的快速热退火方法，其包括以下步骤：在器件电参数，退火温度和STI分布密度之间建立三元对应关系; 导出半导体器件的特定区域中的STI分布密度和目标STI分布密度; 确定特定区域中的STI分布密度是否大于目标STI分布密度; 如果特定区域中的STI分布密度大于目标STI分布密度，则在特定区域中添加虚拟结构，使得特定区域中的STI分布密度等于目标STI分布密度; 并从三元对应关系导出与目标STI分布密度相对应的目标退火温度，并且在半导体器件上执行具有退火温度的退火处理以实现目标电参数。该方法可以减轻快速热退火处理的温度不均匀现象，以避免对半导体器件的电气性能的任何影响。

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