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1. 发明授权

US4437183A Method and apparatus for distributing control signals 失效
标题翻译：用于分配控制信号的方法和装置
公开(公告)号：US4437183A
公开(公告)日：1984-03-13
申请号：US224340
申请日：1981-01-12
申请人： Gary A. Profet
发明人： Gary A. Profet
IPC分类号： H04J3/12
CPC分类号： H04J3/12
摘要： A method and apparatus are described in which the control signals for a data channel are transmitted along with the channel aaddress. The control signal and its address are transmitted on a bit interleaved basis in response to CONTROL select signals that are generated as part of the frame. In accordance with the invention, the CONTROL select signals are distributed relatively uniformly throughout the frame. At the receiver, the bits of the control signal and its address are reassembled and the address is used to route the control signal to its proper channel. Further, the bandwidth assigned to control signaling is increased by inserting CONTROL select signals in all time slots that are available in the frame after the necessary channel select signals and other overhead select signals have been assigned. This technique is particularly advantageous in a system having a fixed aggregate transmission bandwidth, variable loads and the capability of automatically reconfiguring the frame.
摘要翻译：描述了一种方法和装置，其中用于数据信道的控制信号与信道地址一起发送。响应于作为帧的一部分生成的控制选择信号，控制信号及其地址以比特交织的方式发送。根据本发明，控制选择信号在整个帧中相对均匀地分布。在接收机处，重新组合控制信号及其地址的位，并将该地址用于将控制信号路由到其适当的信道。此外，通过在必须的信道选择信号和其他开销选择信号被分配之后，在帧中可用的所有时隙中插入CONTROL选择信号来增加分配给控制信令的带宽。该技术在具有固定的总体传输带宽，可变负载和自动重新配置帧的能力的系统中是特别有利的。

2. 发明授权

US4039751A Method and apparatus for closed loop testing of first and second modulators and demodulators 失效
标题翻译：第一和第二调制器和解调器闭环测试的方法和装置
公开(公告)号：US4039751A
公开(公告)日：1977-08-02
申请号：US668990
申请日：1976-03-22
申请人： Robert A. Couturier , Steven J. Davis , G. Howard Robbins
发明人： Robert A. Couturier , Steven J. Davis , G. Howard Robbins
IPC分类号： H04J1/14 , H04L1/24 , H04M11/06 , H04B3/46
CPC分类号： H04M11/06 , H04J1/14 , H04L1/243
摘要： A method and apparatus are disclosed for closed loop testing of first and second modulators and demodulators from the modulated signal side of the first modulator and first demodulator. During ordinary communication, the first modulator and second demodulator are connected in series and the first demodulator and the second modulator are connected in series. In response to each test initiate signal, a loop is established between the second modulator and the second demodulator on their modulated signal side. Upon reception of some test initiate signals, a loop is established between the first modulator and first demodulator on their demodulated side and they are disconnected from the second demodulator and second modulator. Thus, the first modulator and demodulator can be tested from their modulated signal side when a loop is established between them; and the first and second modulators and demodulators can be tested when a loop is established between the second modulator and demodulator but not between the first modulator and demodulator.

3. 发明授权

US4839542A Active transconductance filter device 失效
标题翻译：有源跨导滤波器
公开(公告)号：US4839542A
公开(公告)日：1989-06-13
申请号：US642912
申请日：1984-08-21
申请人： Jeffrey I. Robinson
发明人： Jeffrey I. Robinson
IPC分类号： G06G7/184 , H03H11/04
CPC分类号： H03H11/045 , G06G7/184
摘要： An integrator is described that is useful in forming low pass, band pass, high pass, and band stop filters. The integrator comprises a transconductance amplifier and a capacitor which is connected between the amplifier output terminal and the amplifier ground. When implemented as a monolithic IC, the integrator gain is fundamentally process independent. A ladder structure comprising one or more of these integrators provides high order filtering characteristics without many of the problems associated with conventional filter devices. In addition, the integrator provides stop band, zero filter characteristics at the filter output terminal when a capacitor is connected across the differential input terminals of the integrator.
摘要翻译：描述了在形成低通，带通，高通和带阻滤波器中有用的积分器。积分器包括跨导放大器和连接在放大器输出端子和放大器接地之间的电容器。当实现为单片IC时，积分器的增益基本上与流程无关。包括这些积分器中的一个或多个的梯形结构提供高阶滤波特性，而没有与常规滤波器装置相关的许多问题。此外，当积分器的差分输入端子连接电容器时，积分器在滤波器输出端子处提供阻带，零滤波器特性。

4. 发明授权

US4803654A Circular first-in, first out buffer system for generating input and output addresses for read/write memory independently 失效
标题翻译：循环先进先出缓冲系统，用于独立生成读/写存储器的输入和输出地址
公开(公告)号：US4803654A
公开(公告)日：1989-02-07
申请号：US747095
申请日：1985-06-20
申请人： Joseph D. Rasberry , Karl D. Nitschke
发明人： Joseph D. Rasberry , Karl D. Nitschke
IPC分类号： G06F5/10 , G06F12/02
CPC分类号： G06F5/10
摘要： A circulating FIFO buffer eliminates the need to move the data through the register and relies instead on input and output counters to load data into the register and read data therefrom. Apparatus comprises an addressable read/write memory, an input counter and an output counter, both of which address the memory, means for resetting the counters, means for enabling the input counter to increment and to load data into the buffer, means for enabling the output counter after a predetermined amount of data has been loaded into the buffer, means for disabling the input counter when the buffer register has been loaded and means for detecting when the outputs of the output and input counters are equal and for activating the resetting means upon detecting such equality.
摘要翻译：循环FIFO缓冲器不需要通过寄存器移动数据，而是依靠输入和输出计数器将数据加载到寄存器中并从中读取数据。装置包括可寻址读/写存储器，输入计数器和输出计数器，两者都对存储器寻址，用于复位计数器的装置，用于使输入计数器增加并将数据加载到缓冲器的装置，在预定量的数据被加载到缓冲器之后的输出计数器，当缓冲寄存器被加载时禁止输入计数器的装置和用于检测输出和输入计数器的输出何时相等并用于激活复位装置的装置检测这种平等。

5. 发明授权

US4413350A Programmable clock rate generator 失效
标题翻译：可编程时钟速率发生器
公开(公告)号：US4413350A
公开(公告)日：1983-11-01
申请号：US224336
申请日：1981-01-12
申请人： William C. Bond , Gary A. Profet
发明人： William C. Bond , Gary A. Profet
IPC分类号： G04G3/02 , H03K23/66 , G06M3/00 , H03K21/36
CPC分类号： H03K23/66 , G04G3/022
摘要： A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.
摘要翻译：描述了一种时钟速率发生器，其可以被编程以提供N / M倍的标准时钟的N / M倍的输出时钟速率，其中N和M是整数。发生器包括计数器，可编程存储器，复位逻辑和时钟控制。一个标准时钟被加到计数器上，这样每个时钟位的计数器就会被提前一个。计数器的输出连接到可编程存储器的输入行，其中存储了二进制和零的模式。可编程存储器的输出被施加到时钟控制以组合相同极性的连续位。除数M由计数器的连续复位之间的标准时钟计数的数量决定。乘法器N由计数器的连续复位之间的时钟控制的输出周期数决定。

6. 发明授权

US4471489A Automatic answer/originate mode selection in modem 失效
标题翻译：调制解调器中自动应答/发起方式选择
公开(公告)号：US4471489A
公开(公告)日：1984-09-11
申请号：US245549
申请日：1981-03-19
申请人： Kenneth Konetski , David M. Moon
发明人： Kenneth Konetski , David M. Moon
IPC分类号： H04M11/06
CPC分类号： H04M11/06
摘要： A method and apparatus are described for automatically placing a modem in the answer or originate mode of operation without the use of a ring detector or a manually operated answer/originate mode selection switch. A timer and two latches are connected in the modem in such a fashion that when the modem is switched into operation it is in the originate mode. For a period of time determined by the timer, the modem looks for the receipt of an answer tone from a remotely located modem. If the answer tone is detected within this time, the modem remains in the originate mode and completes a handshaking sequence with the remote modem. If, however, the answer tone is not received, the modem automatically switches to the answer mode of operation and transmits an answer tone as part of the handshaking sequence.
摘要翻译：描述了一种方法和装置，用于在不使用环形检测器或手动操作的应答/起始模式选择开关的情况下自动将调制解调器放置在应答或发起操作模式中。定时器和两个锁存器以调制解调器的方式连接，当调制解调器切换到操作状态时，它处于起始模式。在由定时器确定的时间段内，调制解调器从远程调制解调器寻找应答音的接收。如果在此时间内检测到应答音，则调制解调器保持原始模式，并使用远程调制解调器完成握手序列。然而，如果未接收到应答音，则调制解调器自动切换到应答操作模式，并且作为握手序列的一部分发送应答音。

7. 发明授权

US4460993A Automatic framing in time division multiplexer 失效
标题翻译：时分复用器自动成帧
公开(公告)号：US4460993A
公开(公告)日：1984-07-17
申请号：US224339
申请日：1981-01-12
申请人： Dean A. Hampton , David A. Lambert
发明人： Dean A. Hampton , David A. Lambert
IPC分类号： H04J3/06 , H04J3/16 , H04L5/22
CPC分类号： H04L5/22 , H04J3/1647
摘要： A method and apparatus are described for automatically generating the frame that is used in a bit-interleaved time division multiplexer (TDM). The apparatus comprises a microprocessor, two random access memories in which are stored the channel select signals, device for determining the transmission frequencies of each channel and a computer program which is stored in the memory of the computer for calculating the distribution of the channel select signals in the frame. With such a system, the frame can be reconfigured in about thirty seconds. Two random access memories are preferably used for the storage of the channel select signals. While the signals stored in one memory are being used to generate the actual frame, a new set of channel select signals can be stored in the other memory. After such an updated frame is written in the second memory, the task of generating the channel select signals can be switched from the first memory to the second memory without loss of any data from any of the data channels.
摘要翻译：描述了一种用于自动生成在比特交织的时分多路复用器（TDM）中使用的帧的方法和装置。该装置包括微处理器，其中存储有信道选择信号的两个随机存取存储器，用于确定每个通道的传输频率的装置和存储在计算机的存储器中用于计算信道选择信号的分布的计算机程序在框架中。利用这样的系统，帧可以在大约三十秒内重新配置。优选地，两个随机存取存储器用于存储信道选择信号。当存储在一个存储器中的信号被用于产生实际的帧时，一组新的信道选择信号可以存储在另一个存储器中。在这样的更新的帧被写入第二存储器之后，产生通道选择信号的任务可以从第一存储器切换到第二存储器，而不会丢失任何数据通道的任何数据。

8. 发明授权

US4412141A Three state loop keyer 失效
标题翻译：三态循环键控
公开(公告)号：US4412141A
公开(公告)日：1983-10-25
申请号：US217098
申请日：1980-12-16
申请人： Christian C. Jacobsen
发明人： Christian C. Jacobsen
IPC分类号： H03K17/66 , H03K17/04 , H03K17/28
CPC分类号： H03K17/667
摘要： A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor. When the AND gate is enabled and the output signal from the exclusive OR gate is the oscillator output signal, only one of these transistors is switched ON; and when the output of the oscillator gate is the inverted signal only the other transistor is switched ON. When the AND gate is disabled, neither transistor is switched on. For polar operation of this circuit, the opposite end of the transmission line is connected through a load resistor to voltage supply common. For neutral operation either the AND gate can be enabled and disabled or the load resistor can be connected to voltage supply positive or negative.
摘要翻译：描述了提供极性和中性接口的晶体管化键控电路。该电路包括振荡器，与门，异或门，变压器和两个类似的输出电路，每个都连接到变压器的次级。振荡器产生具有不对称占空比的高频二进制输出信号。振荡器的输出和低频数据信号被施加到与门。与门和另一个低频数据信号的输出被施加到异或门，该异或门的输出被放大并施加到变压器的初级。耦合到变压器的次级的每个输出电路包括用于将电源电压切换到传输线上的开关晶体管和用于控制开关晶体管的操作的峰值检测器。当与门使能并且异或门的输出信号是振荡器输出信号时，这些晶体管中只有一个接通; 当振荡器门的输出为反相信号时，只有另一个晶体管导通。当与门禁用时，晶体管都不会导通。对于该电路的极性运算，传输线的相对端通过负载电阻连接到电源电压。对于中性运行，与门可以使能和禁止，或负载电阻可以连接到电源正或负。

9. 发明授权

US4394767A Data transmission over long distance circuits 失效
标题翻译：长途电话数据传输
公开(公告)号：US4394767A
公开(公告)日：1983-07-19
申请号：US281059
申请日：1981-07-07
申请人： Martin N. Y. Shum
发明人： Martin N. Y. Shum
IPC分类号： H04B3/20 , H04L5/16
CPC分类号： H04B3/20 , H04L5/16
摘要： A method and apparatus are disclosed which provide a common handshaking protocol for the 201, 202 and 208 modems. In accordance with the invention, connection of answer modem and originate modem to the communication line is followed by a period of silence that is sufficiently long to reactivate any echo suppressors in the communication line. Thereafter at least two training sequences are transmitted, one from the originate modem to the answer modem and the other from the answer modem to the originiate modem, each training sequence being sufficiently long to train up any echo canceller in the line. The lengths of the training sequences as received are compared with their lengths as transmitted to determine if the length of the sequence was shortened by an echo suppressor. If the length of the training sequences as received are significantly shorter than their lengths as transmitted, a sacrificial carrier is transmitted at the beginning of each transmission of data in a new direction. In the event the training sequences as received are not significantly shorter, each transmission of data in a new direction begins without a sacrificial carrier. As a result, greater data throughput can be achieved in the absence of echo suppressors and errors can be avoided while echo cancellers are being trained.
摘要翻译：公开了一种为201,202和208调制解调器提供公共握手协议的方法和装置。根据本发明，应答调制解调器和起始调制解调器到通信线路的连接后面是一个沉默期，足够长的时间来重新激活通信线路中的任何回波抑制器。此后，发送至少两个训练序列，一个从起始调制解调器到应答调制解调器，另一个从应答调制解调器发送到发起调制解调器，每个训练序列足够长以训练该线中的任何回波消除器。将接收到的训练序列的长度与其发送的长度进行比较，以确定序列的长度是否被回波抑制器缩短。如果接收到的训练序列的长度明显短于其所传输的长度，则在每个新数据传输开始时传送牺牲载波。在接收到的训练序列不会明显缩短的情况下，新的方向上的数据的每次传输都不需要牺牲载波。因此，在没有回波抑制器的情况下可以实现更大的数据吞吐量，并且可以避免回波消除器被训练时的错误。

10. 发明授权

US4095045A Method and apparatus for signaling in a communication system 失效
标题翻译：用于在通信系统中进行信号的方法和装置
公开(公告)号：US4095045A
公开(公告)日：1978-06-13
申请号：US760666
申请日：1977-01-19
申请人： Charles P. Johnson , Frederick A. Lucas
发明人： Charles P. Johnson , Frederick A. Lucas
IPC分类号： H04L29/10 , G06F13/38 , H04L5/14 , H04L5/16 , H04L12/00 , H04L13/18 , H04L11/00
CPC分类号： H04L12/00 , G06F13/38
摘要： A method and apparatus are disclosed for using a specified pattern of signal events for signaling in a digital communication system. Illustratively, detection of a first event in a control signal activates timing apparatus which looks for a second event in a control signal within a specified time "window" and at least one additional event in either a data or a control signal within a specified time period. Preferably, the first event is a drop in one of the carrier detect or request to send signals and the second event is a rise in the same signal. The additional event illustratively is reception of two identical data characters, each representing an address and an operation code. Each of these two characters must be received and compared for verification within the specified time period in order to produce an output control signal decoded from the operation code. This signal may be used for any application such as the activation of a terminal to receive data, the initiation of a test sequence, or a change of the network configuration.

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