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1. 发明公开

KR1020100079065A 상호 연결을 고려한 소자의 설계 방법 无效
标题翻译：用反射互连设计设备的方法
公开(公告)号：KR1020100079065A
公开(公告)日：2010-07-08
申请号：KR1020080137476
申请日：2008-12-30
申请人： 주식회사 디비하이텍
发明人： 이종섭
IPC分类号： H01L27/04 , G06F17/50
摘要： PURPOSE: A design method of device offers the simplified interconnection model in consideration of the matter in which the stages for to designing of device become with interconnection. The whole design time is shortened. CONSTITUTION: The capacitance data for to designing about capacitance per resistance data about the metal sheet resistance of device and unit duration receive(10). Concatenated data toward the interconnection of the stages included in device receives(12). Concatenated data is reflected respectively to resistance data and capacitance data(14). The total capacitance about the total resistance value about resistance data and capacitance data calculate. Model is composed by using the total resistance value and total capacitance.
摘要翻译：目的：设备的设计方法考虑到设备的设计阶段变为互连的问题，提供了简化的互连模型。整个设计时间缩短。构成：用于设计关于器件金属片电阻和单位持续时间的电阻数据的电容数据（10）。连接到设备中的级联的连接数据接收（12）。连续数据分别反映给电阻数据和电容数据（14）。关于电阻数据和电容数据的总电阻值的总电容计算。型号由总电阻值和总电容组成。

2. 发明公开

KR1020110078870A 합산기 无效
标题翻译： ADDER
公开(公告)号：KR1020110078870A
公开(公告)日：2011-07-07
申请号：KR1020090135782
申请日：2009-12-31
申请人： 주식회사 디비하이텍
发明人： 이종섭
IPC分类号： G06F7/50 , G06F9/305 , G06F1/04
CPC分类号： G06F7/503 , G06F1/12 , H03K19/08
摘要： PURPOSE: An adder is provided to prevent timing fault effects which can occur by an XNOR or XOR gate included in the output end of CLA and CSA. CONSTITUTION: An adder comprises a CLA(Carry-Lookahead-Adder) block, a CSA(Conditional-Sum-Adder) block, and a dynamic logic circuit. A source area and a drain area are connected to the out signal line of the CLA block, the CSA block, and the dynamic logic circuit. A gate area is connected to a power line or a grounding wire. Therefore, the adder synchronizes an output signal with clock.
摘要翻译：目的：提供一个加法器来防止由CLA和CSA的输出端包含的XOR或XOR门引起的定时故障影响。构成：加法器包括CLA（携带前加加器）块，CSA（条件求和加法器）块和动态逻辑电路。源极区域和漏极区域连接到CLA块，CSA块和动态逻辑电路的输出信号线。门区域连接到电源线或接地线。因此，加法器将输出信号与时钟同步。

3. 发明公开

KR1020110072145A 반도체 소자 메크로 모델 구조 无效
标题翻译：半导体器件的宏模型结构
公开(公告)号：KR1020110072145A
公开(公告)日：2011-06-29
申请号：KR1020090128968
申请日：2009-12-22
申请人： 주식회사 디비하이텍
发明人： 이종섭
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/405 , H01L2027/11868
摘要： PURPOSE: A macro model structure of a semiconductor device is provided to improve the accuracy of an on resistance by respectively adding a parasitic resistance to a drain and a source even through the total width of an LDMSO(Laterally Double Diffused Metal Oxide Semiconductor) increases. CONSTITUTION: A macro model structure of a semiconductor device includes a first parasitic resistance(20) and a variable resistance(10) at a drain and a second parasitic resistance at a source. The variable resistance depends on a voltage between the gate and source and a voltage between the drain and source. The gate is comprised of a poly gate with a plurality of fingers. The values of the first and second parasitic resistances are set according to the surface resistance of metal connecting sources and metal connecting drains in a semiconductor, the number of fingers, the pitch between fingers, and the width of each finger.
摘要翻译：目的：提供半导体器件的宏观模型结构，即使通过LDMSO（双向双扩散金属氧化物半导体）的总宽度分别增加对漏极和源极的寄生电阻来提高导通电阻的精度。构成：半导体器件的宏观模型结构包括漏极处的第一寄生电阻（20）和可变电阻（10）以及源极处的第二寄生电阻。可变电阻取决于栅极和源极之间的电压以及漏极和源极之间的电压。门由具有多个手指的多门构成。第一和第二寄生电阻的值根据金属连接源和半导体中的金属连接漏极的表面电阻，手指的数量，手指之间的间距以及每个手指的宽度来设定。

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