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    • 4. 发明公开
    • 트래핑 설정을 차단하기 위한 장치 및 방법
    • 装置和破碎装置的方法
    • KR1020140001069A
    • 2014-01-06
    • KR1020120116522
    • 2012-10-19
    • 엘에스아이 코포레이션
    • 한양양샤오후아장판리종왕
    • H03M13/03
    • H03M13/6331H03M13/1142H03M13/2957H03M13/3723
    • An error correction data processing device includes: a noise prediction correction circuit capable of operating to correct a first filter coefficient set based on a first data set and a second filter coefficient set based on a second data set; and a first noise prediction detector capable of operating to receive the first filter coefficient set. The device further includes a decoder capable of performing a first global repetition with the first noise prediction detector and operating to decide a violation check count value; and a second noise prediction detector capable of operating to receive the second filter coefficient set when the violation check count value is smaller than a predetermined value, and operating to receive the first filter coefficient set when the violation check count value is greater than the predetermined value. [Reference numerals] (150,125) Detector; (210) Loading; (215) Pingpong shadow register 1; (220) Pingpong shadow register 2; (AA) Bus; (BB) Selecting a selector for controlling Set 1 and Set 2 of NPCAL; (CC) Violation check count from a first global; (DD) Threshold value; (EE) Toward backend DETS
    • 纠错数据处理装置包括:噪声预测校正电路,能够基于第一数据组和基于第二数据组的第二滤波器系数集来校正第一滤波器系数集; 以及能够操作以接收第一滤波器系数组的第一噪声预测检测器。 该装置还包括能够与第一噪声预测检测器执行第一全局重复并操作以确定违反检查计数值的解码器; 以及第二噪声预测检测器,其能够在违反检查计数值小于预定值时操作以接收第二滤波器系数组,并且当违反检查计数值大于预定值时操作以接收第一滤波器系数组 。 (附图标记)(150,125)检测器; (210)装载; (215)乒乓影子寄存器1; (220)乒乓影子寄存器2; (AA)巴士; (BB)选择用于控制NPCAL的Set 1和Set 2的选择器; (CC)来自第一个全球的违规检查数; (DD)阈值; (EE)向后端DETS
    • 5. 发明公开
    • 비순서 데이터 리포팅을 위한 시스템 및 방법
    • 用于订单数据报告的系统和方法
    • KR1020130101453A
    • 2013-09-13
    • KR1020130013042
    • 2013-02-05
    • 엘에스아이 코포레이션
    • 양샤오후아장판한양
    • G11B20/10
    • H04L1/0052G11B20/10527G11B2020/1062G11B2020/185G11B2220/2516H03M13/2957H03M13/6343H04L1/005
    • PURPOSE: A system and a method for an out-of-sequence data reporting capable of processing data are provided to enable a limited out-of-sequence data reporting to be performed. CONSTITUTION: A system of data processing includes a data processing circuit (300) and an out-of-sequence enabling circuit (339). The data processing circuit receives a first received data set, a second received data set, and a third received data set, and can be operated so as to apply data processing algorism to the first, second, third received data sets in order to calculate the first, second, third output data sets. When the second output data set is provided prior to the first output data set, the out-of-sequence enabling circuit can be operated to assert an order indicator output so as to present that the second output data set is out of order. [Reference numerals] (305) Analogue input; (310) Analogue front end circuit; (314) Analogue digital conversion circuit; (320) DFIR circuit; (330) Data detector circuit; (339) Non-order enabling circuit; (342) Local interleaver circuit; (344) Local de-interleaver circuit; (347) Order displayer; (349) Span displayer; (350) Main memory circuit; (353) Input buffer; (361) Maximum queue; (370) Data decoding circuit; (380) De-interleaver circuit; (384) Global interleaver/de-interleaver circuit; (390) Hard decision output circuit; (392) Hard decision output
    • 目的:提供能够处理数据的失序数据报告的系统和方法,以便能够执行有限的失序数据报告。 构成:数据处理系统包括数据处理电路(300)和失序使能电路(339)。 数据处理电路接收第一接收数据组,第二接收数据组和第三接收数据组,并且可以操作以将数据处理算法应用于第一,第二和第三接收数据集,以便计算 第一,第二,第三输出数据集。 当在第一输出数据集之前提供第二输出数据组时,可以操作失序使能电路以断言指令指示符输出,以便呈现第二输出数据集失效。 (附图标记)(305)模拟输入; (310)模拟前端电路; (314)模拟数字转换电路; (320)DFIR电路; (330)数据检测电路; (339)无序使能电路; (342)局部交织电路; (344)局部解交织电路; (347)订单显示; (349)跨度显示器; (350)主存储电路; (353)输入缓冲器; (361)最大队列; (370)数据解码电路; (380)去交织电路; (384)全局交织器/解交织器电路; (390)硬判决输出电路; (392)硬决策输出