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1. 发明公开

KR1020010088178A 반도체 소자의 제조 방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010088178A
公开(公告)日：2001-09-26
申请号：KR1020000012263
申请日：2000-03-11
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석
IPC分类号： H01L21/28
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to improve junction leakage, by performing a process for forming profiled groove isolation(PGI) after silicide is formed, so that field loss doesn't occur because the field is formed after the silicide is formed. CONSTITUTION: A salicide process is performed on a substrate(201) having a gate electrode and a source/drain region(206). A trench is formed in the substrate between the gate electrodes. The first insulation layer(209) and the second insulation layer are sequentially formed on the entire surface including the trench, and a planarization process is performed to form an isolation region of a groove type to improve step coverage with the gate electrode. A conductive material is formed on the gate electrode. The third insulation layer is formed on the entire surface of the substrate, and a contact hole is formed to expose a predetermined portion of the source/drain region. A plug is formed inside the contact hole, and a metal interconnection(213) is formed on the plug.
摘要翻译：目的：提供一种制造半导体器件的方法以通过在形成硅化物之后执行形成型槽隔离（PGI）的工艺来改善结漏电，从而在硅化物为硅化物之后形成场，不会发生场损耗形成。构成：在具有栅极电极和源极/漏极区域（206）的衬底（201）上执行自对准硅化物工艺。在栅电极之间的衬底中形成沟槽。第一绝缘层（209）和第二绝缘层依次形成在包括沟槽的整个表面上，并且进行平坦化处理以形成沟槽类型的隔离区域，以改善栅电极的台阶覆盖。在栅电极上形成导电材料。第三绝缘层形成在基板的整个表面上，并且形成接触孔以暴露源极/漏极区域的预定部分。在接触孔内部形成有插头，在插头上形成有金属配线（213）。

2. 发明授权

KR100451756B1 반도체소자및그제조방법 失效
公开(公告)号：KR100451756B1
公开(公告)日：2004-11-16
申请号：KR1019980034292
申请日：1998-08-24
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석 , 박성형
IPC分类号： H01L21/71
摘要： PURPOSE: The method reduces the junction leakage in salicide process by preventing the revealing of a substrate in the boundary between an active and a field area due to the loss of an isolation in etch back process, and improves the reliability of a device by preventing the destruction of a source/drain impurity region by depositing a nitride film before forming the source/drain impurity region. CONSTITUTION: The semiconductor device includes; a semiconductor substrate(31) defined as an active area and a field area; an isolation(32) formed in STI(Shallow Trench Isolation) structure with a step on the active surface and the field top part of the semiconductor substrate; a gate electrode(34a) formed by intervening a gate insulation film(33) on the active area separated by the isolation; a first side wall(34b) formed on both sides of the gate electrode; a second side wall(36) formed on both sides both sides of the semiconductor substrate revealed by the step of the isolation; a source/drain impurity region(37) formed on the semiconductor substrate on both sides of the gate electrode; and a salicide film(38) formed on the surface of the gate electrode and on the surface of the second side wall and the semiconductor substrate where the source/drain impurity region is formed; and an insulation film(39) which has a contact hole(40) to reveal some of the surface of the salicide film where the source/drain impurity region is formed and is formed on the front of the semiconductor substrate.
摘要翻译：目的：该方法通过防止由于回蚀工艺中的隔离损失而导致活性区和场区之间的边界中的衬底暴露，从而减少了自对准硅化物工艺中的结漏电，并且通过防止通过在形成源极/漏极杂质区之前沉积氮化物膜来破坏源极/漏极杂质区。构成：半导体器件包括：半导体衬底（31），其被定义为有源区域和场区域; 在STI（浅沟槽隔离）结构中形成的隔离层（32），其在半导体衬底的有源表面和场顶部上具有台阶; 通过在由隔离分离的有源区上插入栅绝缘膜（33）而形成的栅电极（34a）形成在所述栅电极的两侧上的第一侧壁（34b）第二侧壁（36），形成在通过所述隔离步骤露出的所述半导体衬底的两侧上; 在栅电极两侧的半导体衬底上形成的源/漏杂质区（37）以及形成在所述栅极电极的表面上以及所述第二侧壁的表面和形成有所述源极/漏极杂质区域的所述半导体基板上的自对准硅化物膜（38）和具有接触孔（40）的绝缘膜（39），以暴露硅化物膜的形成有源极/漏极杂质区的一些表面，并形成在半导体衬底的正面上。

3. 发明授权

KR100437645B1 반도체장치의 제조방법 失效
公开(公告)号：KR100437645B1
公开(公告)日：2004-10-14
申请号：KR1019980008491
申请日：1998-03-13
申请人： 에스케이하이닉스 주식회사
发明人： 이기민 , 윤기석
IPC分类号： H01L29/78
摘要： PURPOSE: A method for manufacturing a semiconductor device is provided to simplify manufacturing process by forming simultaneously an insulating spacer and a passivation layer at cell and peripheral regions, respectively. CONSTITUTION: Gate electrodes(204,204-1) are formed on a cell region(III) and a peripheral region(IV) of a substrate(200). A source/drain region(210-1) is formed in the substrate of the peripheral region. An insulating spacer(208) is formed at both sidewalls of the gate electrode of the cell region and a passivation layer(212-1) is simultaneously formed on the resultant structure of the peripheral region. By implanting dopants into the substrate of the cell region, a source/drain region(210) including an LDD(Lightly Doped Drain)(L-2) is formed. A salicide layer(220) is formed on the substrate and the gate electrode of the cell region.

4. 发明授权

KR100339422B1 반도체 소자의 제조 방법 失效
公开(公告)号：KR100339422B1
公开(公告)日：2002-06-01
申请号：KR1020000012263
申请日：2000-03-11
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석
IPC分类号： H01L21/28
摘要： 본 발명은 실리사이드 형성 이후에 필드를 형성함으로서 필드의 손실을 줄여 정션 리키지를 개선하기 위한 반도체 소자의 제조 방법에 관한 것으로, 게이트 전극 및 소오스/드레인 영역이 형성된 기판상에 살리사이드 공정을 진행하는 단계와, 상기 게이트 전극 사이의 기판에 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 전면에 제 1 절연막, 제 2 절연막을 차례로 형성하고 상기 게이트 전극과 단차가 없도록 평탄화하여 그루브형상의 격리 영역을 형성하는 단계와, 상기 게이트 전극상에 전도성 물질을 형성하는 단계와, 상기 기판 전면에 제 3 절연막을 형성하고, 소오스/드레인 영역이 일정 부분 노출되도록 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 플러그를 형성하고, 상기 플러그상에 금속 배선을 형성하는 단계를 포함하여 이루어지는 � ��을 특징으로 한다.

5. 发明公开

KR1020000039158A 반도체 장치의 정전방전 방지 트랜지스터 제조방법 无效
标题翻译：制造半导体器件静电放电保护晶体管的方法
公开(公告)号：KR1020000039158A
公开(公告)日：2000-07-05
申请号：KR1019980054404
申请日：1998-12-11
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석 , 이기민
IPC分类号： H01L27/06
摘要： PURPOSE: A method for fabricating an electrostatic discharge protection transistor of a semiconductor device is provided to fabricate heavy doped source and drain. CONSTITUTION: A method for fabricating an electrostatic discharge protection transistor comprises defining a cell region and an electrostatic discharge(ESD) protection region, forming gates(3) and lightly doped source and drain(4) on the regions, forming a photoresist pattern on the cell region, transforming the lightly doped source and drain(4) on the ESD protection region to heavily doped source and drain(6), removing the photoresist pattern, forming a nitride(7) pattern on the ESD protection region, forming sidewalls(5) on the side of the gate of the cell region, forming heavily doped source and drain(6) around the sidewalls, forming silicide(8).
摘要翻译：目的：提供一种用于制造半导体器件的静电放电保护晶体管的方法，以制造重掺杂源极和漏极。构成：制造静电放电保护晶体管的方法包括限定电池区域和静电放电（ESD）保护区域，在该区域上形成栅极（3）和轻掺杂源极和漏极（4），在该区域上形成光致抗蚀剂图案将ESD保护区上的轻掺杂源极和漏极（4）转换成重掺杂的源极和漏极（6），去除光致抗蚀剂图案，在ESD保护区域上形成氮化物（7）图案，形成侧壁（5 ），在单元区域的栅极侧，在侧壁周围形成重掺杂的源极和漏极（6），形成硅化物（8）。

6. 发明公开

KR1020000014736A 반도체소자및그제조방법 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020000014736A
公开(公告)日：2000-03-15
申请号：KR1019980034292
申请日：1998-08-24
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석 , 박성형
IPC分类号： H01L21/71
摘要： PURPOSE: The method reduces the junction leakage in salicide process by preventing the revealing of a substrate in the boundary between an active and a field area due to the loss of an isolation in etch back process, and improves the reliability of a device by preventing the destruction of a source/drain impurity region by depositing a nitride film before forming the source/drain impurity region. CONSTITUTION: The semiconductor device includes; a semiconductor substrate(31) defined as an active area and a field area; an isolation(32) formed in STI(Shallow Trench Isolation) structure with a step on the active surface and the field top part of the semiconductor substrate; a gate electrode(34a) formed by intervening a gate insulation film(33) on the active area separated by the isolation; a first side wall(34b) formed on both sides of the gate electrode; a second side wall(36) formed on both sides both sides of the semiconductor substrate revealed by the step of the isolation; a source/drain impurity region(37) formed on the semiconductor substrate on both sides of the gate electrode; and a salicide film(38) formed on the surface of the gate electrode and on the surface of the second side wall and the semiconductor substrate where the source/drain impurity region is formed; and an insulation film(39) which has a contact hole(40) to reveal some of the surface of the salicide film where the source/drain impurity region is formed and is formed on the front of the semiconductor substrate.
摘要翻译：目的：该方法通过防止由于在回蚀工艺中的隔离损失而导致在有源场和场区之间的边界中的衬底露出，从而减少了自杀处理过程中的结漏电，并且通过防止在形成源极/漏极杂质区域之前通过沉积氮化物膜来破坏源极/漏极杂质区域。构成：半导体器件包括：定义为有源区域和场区域的半导体衬底（31）; 在STI（浅沟槽隔离）结构中形成的隔离件（32），其具有在半导体衬底的有源表面和场顶部上的台阶; 通过在由隔离物分离的有源区域上插入栅极绝缘膜（33）而形成的栅电极（34a）形成在所述栅电极的两侧的第一侧壁（34b）形成在半导体衬底的两侧的通过隔离步骤而露出的第二侧壁（36）; 源极/漏极杂质区（37），形成在栅电极的两侧上的半导体衬底上; 以及形成在所述栅电极的表面上以及形成所述源/漏杂质区的所述第二侧壁和所述半导体衬底的表面上的自对准硅膜（38）以及绝缘膜（39），其具有接触孔（40），以露出形成有源极/漏极杂质区域并形成在半导体衬底的前面的自对氟硅膜的一些表面。

7. 发明公开

KR1020030001787A 트랜지스터의 제조 방법 失效
标题翻译：制造晶体管的方法
公开(公告)号：KR1020030001787A
公开(公告)日：2003-01-08
申请号：KR1020010037474
申请日：2001-06-28
申请人： 에스케이하이닉스 주식회사
发明人： 이주형 , 윤기석
IPC分类号： H01L27/092
摘要： PURPOSE: A fabrication method of a transistor is provided to prevent a collapse, a TED(Transient Enhanced Diffusion) and a short-channel effect, and to enhance a processing margin by using a spacer of triple structure. CONSTITUTION: A gate oxide layer(33) and a gate electrode(35) are sequentially formed on a substrate(31) having the first and second region(I,II). After forming a buffer layer(37) as the first spacer on the resultant structure, a lightly doped region(39) is formed in the substrate. The second spacer(41) and the third spacer(43) are sequentially formed at both sidewalls of the gate electrode(35) having the buffer layer(37). By using different etching selectivity, the buffer layer(37) as the first spacer and the third spacer(43) is made of a nitride layer, and the second spacer(41) is composed of an oxide layer. Then, the third spacer(43) of the first region(I) is selectively removed. A graded source/drain region(47) is formed in the first region(I) by implanting dopants using the buffer layer(41) and the second spacer(41) as a mask, and a source/drain region(49) of LDD structure is formed in the second region(II) by using the triple spacer(37,41,43).
摘要翻译：目的：提供晶体管的制造方法以防止塌陷，TED（瞬态增强扩散）和短沟道效应，并通过使用三重结构的间隔来增强处理裕度。构成：在具有第一和第二区域（I，II）的基板（31）上依次形成栅极氧化物层（33）和栅极电极（35）。在所得结构上形成作为第一间隔物的缓冲层（37）之后，在衬底中形成轻掺杂区域（39）。第二间隔物（41）和第三间隔物（43）依次形成在具有缓冲层（37）的栅电极（35）的两个侧壁处。通过使用不同的蚀刻选择性，作为第一间隔物的缓冲层（37）和第三间隔物（43）由氮化物层构成，第二间隔物（41）由氧化物层构成。然后，选择性地去除第一区域（I）的第三间隔物（43）。通过使用缓冲层（41）和第二间隔物（41）作为掩模注入掺杂剂以及LDD的源极/漏极区域（49），在第一区域（I）中形成分级源极/漏极区域（47）通过使用三重间隔物（37,41,43）在第二区域（II）中形成结构。

8. 发明公开

KR1020010054158A 반도체 소자 제조방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR1020010054158A
公开(公告)日：2001-07-02
申请号：KR1019990054829
申请日：1999-12-03
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석
IPC分类号： H01L21/762
摘要： PURPOSE: A method for fabricating a semiconductor device is provided to solve misaligned contact problems and thereby to prevent junction leakage current. CONSTITUTION: In the method, the first and second trenches are formed in a semiconductor substrate(31) and covered with an insulating layer. Next, a conductive layer is formed thereon and patterned to form the first and second conductive patterns(36,36a) each staying in one side of the trench and protruding above the trench. The rest side of each trench is then filled with a planarized insulating layer(38). Next, not only the first gate electrode(40a) connected to the first conductive pattern(36) but also the second gate electrode(40b) located between the both trenches is formed on the substrate(31). Next, a conductive sidewall(40c) is formed on a confronting side of each conductive pattern(36,36a), and an insulating sidewall(41) is formed on both sides of each gate electrode(40a,40b). Next, a silicide layer(43) is formed on specific areas, including a local interconnection between the first gate electrode(40a) and a source region(42) near the second gate electrode(40b). Next, an insulating layer(44) is wholly formed and patterned to form a borderless contact(46) connected to a portion of the silicide layer(43) above the second trench.
摘要翻译：目的：提供一种用于制造半导体器件的方法，以解决不对准的接触问题，从而防止结漏电流。构成：在该方法中，第一沟槽和第二沟槽形成在半导体衬底（31）中并被绝缘层覆盖。接下来，在其上形成导电层并图案化以形成分别保留在沟槽的一侧并突出在沟槽上方的第一和第二导电图案（36,36a）。然后，每个沟槽的其余侧面被平坦化的绝缘层（38）填充。接下来，不仅在基板（31）上形成与第一导电图案（36）连接的第一栅电极（40a），而且在两沟槽之间形成第二栅电极（40b）。接下来，在每个导电图案（36,36a）的相对侧上形成导电侧壁（40c），并且在每个栅电极（40a，40b）的两侧形成绝缘侧壁（41）。接下来，在特定区域上形成硅化物层（43），包括第一栅极电极（40a）和靠近第二栅电极（40b）的源极区域（42）之间的局部互连。接下来，绝缘层（44）被完全形成并图案化以形成与第二沟槽上方的硅化物层（43）的一部分连接的无边界接触（46）。

9. 发明公开

KR1020040001908A 접합 누설 억제를 위한 반도체 소자 제조방법 失效
标题翻译：通过限制接触漏电来制造半导体器件的方法
公开(公告)号：KR1020040001908A
公开(公告)日：2004-01-07
申请号：KR1020020037242
申请日：2002-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석
IPC分类号： H01L21/336
摘要： PURPOSE: A method for manufacturing a semiconductor device by restraining junction leakage is provided to improve reliability by restraining junction leakage generated at edges of an active region. CONSTITUTION: A field insulating layer(12) is formed at a silicon substrate(10) for defining an active and inactive region. A portion of the field insulating layer(12) adjacent to the active region is selectively removed. A source/drain region(20) is then formed in the active region of the silicon substrate(10) by ion-implantation. At this time, the source/drain region further includes a band-down profile(20A) located at an edge portion of the active region.
摘要翻译：目的：提供一种通过抑制接点泄漏来制造半导体器件的方法，以通过抑制在有源区域的边缘处产生的结泄漏来提高可靠性。构成：在硅衬底（10）处形成场绝缘层（12），用于限定有源和非活性区域。选择性地去除与有源区相邻的场绝缘层（12）的一部分。然后通过离子注入在硅衬底（10）的有源区中形成源/漏区（20）。此时，源极/漏极区域还包括位于有源区域的边缘部分处的带状轮廓（20A）。

10. 发明授权

KR100382984B1 반도체 소자 및 그의 제조 방법 失效
标题翻译： 반도체소자및그의제조방법
公开(公告)号：KR100382984B1
公开(公告)日：2003-05-09
申请号：KR1020000075526
申请日：2000-12-12
申请人： 에스케이하이닉스 주식회사
发明人： 윤기석
IPC分类号： H01L29/78
摘要： PURPOSE: A semiconductor device is provided to reduce gate sheet resistance by increasing a silicide layer on a gate electrode, and to prevent silicide from being lumped by a thermal process for forming a nitride layer by forming a silicide layer as a passivation layer of an isolation layer in a process for forming a contact hole. CONSTITUTION: A semiconductor substrate(31) is of the first conductivity type, wherein the isolation layer(32) is formed in an isolation region of the substrate. A gate electrode(34) is formed in the active region of the semiconductor substrate by interposing a gate insulation layer. An insulation layer sidewall higher than the gate electrode is formed on the semiconductor substrate at both sides of the gate electrode. A source/drain impurity region of the second conductivity type is formed in the semiconductor substrate at both sides of the gate electrode including the insulation layer sidewall. A polycrystalline silicon sidewall(39) is formed in a side of the insulation layer sidewall on the gate electrode and in the interface between the isolation layer and the active region. The silicide layer(40) is formed on the gate electrode, the source/drain impurity region and the polycrystalline silicon sidewall. An interlayer dielectric(41) is formed on the entire surface including the gate electrode, having an interconnection contact hole. An interconnection layer(42) is formed on the interconnection contact hole and the interlayer dielectric adjacent to the interconnection contact hole.
摘要翻译：目的：提供半导体器件以通过增加栅电极上的硅化物层来减少栅极薄层电阻，并且通过形成硅化物层作为隔离的钝化层来防止硅化物被用于形成氮化物层的热过程集中在形成接触孔的过程中形成一层。构成：半导体衬底（31）具有第一导电类型，其中隔离层（32）形成在衬底的隔离区中。通过插入栅绝缘层在半导体衬底的有源区中形成栅电极（34）。在栅电极两侧的半导体衬底上形成高于栅电极的绝缘层侧壁。第二导电类型的源极/漏极杂质区域在包括绝缘层侧壁的栅电极的两侧处形成在半导体衬底中。多晶硅侧壁（39）形成在栅电极上的绝缘层侧壁的一侧以及隔离层和有源区之间的界面中。硅化物层（40）形成在栅电极，源/漏杂质区和多晶硅侧壁上。层间电介质（41）形成在包括栅电极的整个表面上，具有互连接触孔。互连层（42）形成在互连接触孔和与互连接触孔相邻的层间电介质上。

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