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    • 1. 发明公开
    • 이중 구조의 인터럽트선택레지스터를 이용한다중모드복조부와 다중사용자 변조부 간 듀얼포트램인터럽트 처리 방법
    • 使用双结构中断选择寄存器处理多模式解调器板组件和多用户调制器板组件之间的双端口RAM中断的方法
    • KR1020010065121A
    • 2001-07-11
    • KR1019990064935
    • 1999-12-29
    • 에스케이하이닉스 주식회사
    • 노혜경
    • H04B7/155
    • H04W88/08H04B7/155H04W88/10
    • PURPOSE: A method for processing dual port ram interrupt between a multi-mode demodulator board assembly and a multi-user modulator board assembly using a dual-structured interrupt select register is provided to effectively process eight interrupt source with one DSP CPU interrupt without hazard. CONSTITUTION: If external interrupt for DPRAM telecommunication is generated in a MMDA(Multi-Mode Demodulator board Assembly), data of an ISR(Interrupt Select Register) is duplicated to an ISRP(Interrupt Select Register coPy)(ST11-ST14). Data of the ISRP is read for processing interrupt according to the order of enabled interrupt(ST15-ST16). Data of the ISR and data of the ISRP are compared with each other, and if not same, the ISRP is cleared(ST17-ST18). Cleared data of the ISRP and data of the ISR are compared with each other, if all data are not in clear state, data of the ISR is duplicated to the ISRP(ST14). If all data are in clear state, an interrupt routine for DPRAM telecommunication in the MMDA is terminated(ST19).
    • 目的:提供一种在多模式解调器板组合和使用双结构中断选择寄存器的多用户调制器板组合之间处理双端口RAM中断的方法,以有效处理具有一个DSP CPU中断的八个中断源,而无危险。 构成:如果在MMDA(多模式解调器板组件)中产生了DPRAM通信的外部中断,则ISR(中断选择寄存器)的数据被复制到ISRP(中断选择寄存器coPy)(ST11-ST14)。 根据使能中断的顺序(ST15-​​ST16)读取ISRP的数据进行处理中断。 将ISR的数据和ISRP的数据进行比较,如果不相同,则清除ISRP(ST17-ST18)。 将ISRP清除数据和ISR数据进行比较,如果所有数据都不在清除状态,则将ISR的数据复制到ISRP(ST14)。 如果所有数据都处于清除状态,则终止MMDA中的DPRAM电信中断程序(ST19)。
    • 7. 发明公开
    • 직렬 데이터 제어 버스를 이용한 D채널 데이터 정합 장치 및방법
    • 用于匹配D信道数据的方法和装置
    • KR1020010009051A
    • 2001-02-05
    • KR1019990027199
    • 1999-07-07
    • 에스케이하이닉스 주식회사
    • 기경진노혜경
    • H04L12/28
    • PURPOSE: A D channel data matching apparatus is provided to increase transference of the D channel data by realizing a subscriber matching board between a D channel manipulating board and a network terminal. CONSTITUTION: A D channel data matching apparatus comprises a subscriber matching board(200) and a D channel manipulating board(300). The subscriber matching board(200) receives data transferred through a 2B+D channel from a network terminal(100) and divides the received data into B channel data and D channel data. After furnishing of clock and synchronous signals, the B channel data is transferred to a sub highway and a duplicated D channel data is transferred through a serial control bus. The D channel manipulating board(300) receives the B and D channel data from the subscriber matching board(200). The D channel manipulating board(300) bypasses the B channel data to an upper board and packet processes the duplicated D channel data.
    • 目的:提供一种D信道数据匹配装置,通过实现D信道操纵板与网络终端之间的用户匹配板来增加D信道数据的传输。 构成:D信道数据匹配装置包括用户匹配板(200)和D信道操纵板(300)。 用户匹配板(200)接收从网络终端(100)通过2B + D信道传送的数据,并将接收到的数据划分为B信道数据和D信道数据。 在提供时钟和同步信号之后,将B信道数据传送到子公路,通过串行控制总线传送复制的D信道数据。 D信道操纵板(300)从用户匹配板(200)接收B和D信道数据。 D信道操纵板(300)将B信道数据旁路到上层,并且分组处理复制的D信道数据。
    • 8. 发明公开
    • ISDN 교환기내 병렬 데이터 전송에 의한 프래쉬 메모리 데이터퓨징장치 및 그 제어방법
    • 用于基于ISDN开关中的并行数据传输的新鲜存储器数据的装置及其控制方法
    • KR1020000060725A
    • 2000-10-16
    • KR1019990009271
    • 1999-03-18
    • 에스케이하이닉스 주식회사
    • 기경진노혜경
    • H04M3/22
    • PURPOSE: An apparatus for fusing a fresh memory data based on a parallel data transmission in an ISDN switch and a control method of the same are provided to increase a productivity by decreasing an operating program fusing time using a fresh memory installed in a matching circuit pack. CONSTITUTION: A fresh memory data fusing apparatus based on a parallel data transmission of an ISDN switch includes a fresh memory(101), a basic subscriber matched circuit pack(100) formed of a first microprocessor(103) and a first buffer(105), a basic subscriber matched back board(ISBB: ISDN subscriber interface back board)(200), a terminal(300), and a D-channel processor circuit pack(400) formed of a ROM(Read Only Memory)(401), a second microprocessor(403) and a second buffer(405).
    • 目的:提供一种用于在ISDN交换机中基于并行数据传输来融合新鲜存储器数据的装置及其控制方法,以通过使用安装在匹配电路板中的新鲜存储器来减少操作程序融合时间来提高生产率 。 构成:基于ISDN交换机的并行数据传输的新鲜存储器数据融合装置包括新鲜存储器(101),由第一微处理器(103)和第一缓冲器(105)形成的基本用户匹配电路板(100) ,基于用户匹配的背板(ISBB:ISDN用户接口背板)(200),终端(300)和由ROM(只读存储器)(401)形成的D信道处理器电路板, 第二微处理器(403)和第二缓冲器(405)。