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1. 发明公开

KR1020000065927A 전전자교환기의 통화경로시험방법 失效
标题翻译：在全电子切换系统中测试通信模块的方法
公开(公告)号：KR1020000065927A
公开(公告)日：2000-11-15
申请号：KR1019990012692
申请日：1999-04-10
申请人： 에스케이하이닉스 주식회사
发明人： 정정수 , 양태준 , 김길용
IPC分类号： H04Q11/06
摘要： PURPOSE: A method for testing communication paths in the full electronic switching system is provided so that a processor carry out an internal path test and a time switch-space switch-time switch path test of a time switch automatically at the same time. CONSTITUTION: After determining a test period(S1'), a space switch and a first link control processor transmits a test message comprising space switch internal idle channel data to a time switch and a second link control processor(S2'). After receiving the test message, determining a subscriber's idle channel, writing test data to a first time switch and a first link block and setting up a path to the space internal idle channel, the space switch and the second link control processor transmits a path result to the time switch and the first link control processor(S3'). If a path setup result of the time switch and the second link control processor is not normal, the space switch and the second link control processor outputs the result to the terminal. If normal, the space switch and the second link control processor controls the space switch and a second link block and sets up a path. If a path setup result of the space switch and the second link block is not normal, the space switch and the second link control processor outputs the result to the terminal. If normal, the space switch and the second link control processor transmits the test message comprising the space switch internal idle channel data to the time switch and a third control processor(S4').
摘要翻译：目的：提供一种用于测试全电子交换系统中通信路径的方法，以便处理器同时自动执行时间切换的内部路径测试和时间切换空间切换时间切换路径测试。构成：在确定了测试周期（S1'）之后，空间切换器和第一链路控制处理器将包括空间切换内部空闲信道数据的测试消息发送到时间交换机和第二链路控制处理器（S2'）。在接收到测试消息之后，确定用户的空闲信道，将测试数据写入第一时间交换机和第一链路块并建立到空间内部空闲信道的路径，空间交换机和第二链路控制处理器发送路径结果到时间切换和第一链路控制处理器（S3'）。如果时间切换和第二链路控制处理器的路径建立结果不正常，则空间切换器和第二链路控制处理器将结果输出到终端。如果正常，空间切换器和第二链路控制处理器控制空间切换器和第二链路块并建立路径。如果空间切换和第二链路块的路径建立结果不正常，则空间切换器和第二链路控制处理器将结果输出到终端。如果正常，则空间交换机和第二链路控制处理器将包括空间交换机内部空闲信道数据的测试消息发送到时间交换机和第三控制处理器（S4'）。

2. 发明公开

KR1020000059397A 교환기의 다중 프로토콜 기능 장치 失效
标题翻译：交换多协议功能的设备
公开(公告)号：KR1020000059397A
公开(公告)日：2000-10-05
申请号：KR1019990006961
申请日：1999-03-03
申请人： 에스케이하이닉스 주식회사
发明人： 백현수 , 김길용 , 노재웅
IPC分类号： H04Q5/02
摘要： PURPOSE: A device for a multi-protocol function of an exchange is provided to simultaneously receive a V5.2 protocol, an integrated services digital network(ISDN) primary rate access(PRI) protocol and a frame protocol in the exchange to process the multi-protocol in one hardware system. CONSTITUTION: An exchange has a mutual connector, a multi-protocol processor and a subscriber interface. The multi-protocol processor is comprised as follows. An address translator(24) approaches each block without errors by translating addresses of blocks selected by the CPU. An internal time sharing switch(25) switches a channel processing a protocol of each E1 frame to the CPU, and transceives a voice channel to/from the external time sharing switch interface, by switching each E1 frame of the first/fourth E1 framer and line interface. A multi-channel HDLC processor(26) extracts or mixes a channel processing a HDLC protocol in each E1 frame, to transmit to the CPU. An external time sharing switch interface(27) supplies a clock and a frame synchronous signal to the internal time sharing switch, the first/fourth E1 framer and line interface by receiving the signal from the external time sharing switch, and interfaces the external time sharing switch, each E1 trunk and the voice channel. A first/fourth E1 framer and line interface(28,31) generate an E1 frame, divide a received frame, and transmit into a dipole signal level for remote transmission with an E1 link. The multi-protocol processor is further comprised of a CPU(21), a clock generating circuit(22) and a memory(23).
摘要翻译：目的：提供交换机多协议功能的设备，以同时接收V5.2协议，综合业务数字网（ISDN）主速率接入（PRI）协议和交换机中的帧协议，以处理多 - 协议在一个硬件系统。构成：交换机具有互连连接器，多协议处理器和用户接口。多协议处理器包括如下。地址转换器（24）通过翻译由CPU选择的块的地址而无误地接近每个块。内部时分共享交换机（25）将处理每个E1帧的协议的信道切换到CPU，并通过切换第一/第四E1成帧器的每个E1帧和/或从外部时分共享交换机接口收发语音信道，以及线路接口。多通道HDLC处理器（26）提取或混合在每个E1帧中处理HDLC协议的信道，以传送到CPU。外部时间共享切换接口（27）通过接收来自外部时间共享切换器的信号向内部时间共享交换机，第一/第四个E1成帧器和线路接口提供时钟和帧同步信号，并将外部时间共享交换机，每个E1中继线和语音通道。第一/第四E1成帧器和线路接口（28,31）生成E1帧，划分接收到的帧，并发送到具有E1链路的远程传输的偶极信号电平。多协议处理器还包括CPU（21），时钟发生电路（22）和存储器（23）。

3. 发明授权

KR100300843B1 교환기의 다중 프로토콜 기능 장치 失效
标题翻译：交换机多协议能力的装置
公开(公告)号：KR100300843B1
公开(公告)日：2001-09-26
申请号：KR1019990006961
申请日：1999-03-03
申请人： 에스케이하이닉스 주식회사
发明人： 백현수 , 김길용 , 노재웅
IPC分类号： H04Q5/02
摘要： 본발명은교환기의다중프로토콜기능장치를제공하기위한것으로, 이러한본 발명은다중프로토콜처리부와가입자정합부와연결되어가입자가다중프로토콜로접속할수 있도록정합하는상호접속부와; 상기상호접속부와연결되어 E1 물리계층에서 No.7 프로토콜, V5.2 프로토콜, ISDN PRI 프로토콜, 프레임릴레이프로토콜을동시수용하고, 해당프로토콜을처리하는다중프로토콜처리부와; 상기상호접속부와가입자간의인터페이스를수행하여가입자가다중프로토콜기능을사용할수 있도록정합해주는가입자정합부로구성됨으로써, 하나의동일한하드웨어에 4가지프로토콜을처리할수 있으며, 하드웨어를간소화하게구현할수 있다.

4. 发明授权

KR100290661B1 전전자교환기의 통화경로시험방법 失效
标题翻译：全电子交换机测试呼叫路由的方法
公开(公告)号：KR100290661B1
公开(公告)日：2001-05-15
申请号：KR1019990012692
申请日：1999-04-10
申请人： 에스케이하이닉스 주식회사
发明人： 정정수 , 양태준 , 김길용
IPC分类号： H04Q11/06
摘要： 본발명은전전자교환기에서프로세서가타임스위치의내부경로, 타임스위치-스페이스스위치-타임스위치로구성된스위치통화경로및 타임스위치에연결된장치들과의경로를시험하기위한전전자교환기의통화경로시험방법에관한것으로서, 본발명에의한전전자교환기의통화경로시험방법에의하면전전자교환기의타임스위치에통화로시험을위한시험데이터의 2채널쓰기및 읽기즉 홀수및 짝수채널로구분하여쓰기및 읽기가가능하므로타임스위치-스페이스스위치-타임스위치로구성된교환기의스위치경로시험시하나의시험채널은타임스위치의내부경로를또 하나의채널은타임스위치-스페이스스위치-타임스위치경로를시험할수 있어상기두 경로시험을동시에할 수있다는뛰어난효과가있다.

5. 发明公开

KR1020010009052A 상위 프로세서와 중계선 장치간의 데이터 생성 및 전송 방법 无效
标题翻译：用于生成和传输上位处理器和链接线设备之间的数据的方法
公开(公告)号：KR1020010009052A
公开(公告)日：2001-02-05
申请号：KR1019990027200
申请日：1999-07-07
申请人： 에스케이하이닉스 주식회사
发明人： 노재웅 , 김길용
IPC分类号： H04L12/28
摘要： PURPOSE: A data generating and transmitting method is provided to improve upper processor performance without revising of a hardware by reducing the amount of signal data transferred between an upper processor and a link line device. CONSTITUTION: A data generating and transmitting method is described which comprises a transmission algorithm. The transmission algorithm comprises initializing a program for data transmission(S100). A 16-byte data is generated by comparing previous signal data with current signal data in an upper processor(S200). A 2-byte data is generated by comparing the 16-byte data with a set byte number(S300). After transferring the 2-byte data at the upper processor(S400), whether the 16-byte data is transferred is judged according to comparison of the transferred 2-byte data(S500). If the 2-byte data is identical to a set value, the procedure goes to the step(S500). If the 2-byte data is not identical to the set value, varied signal data is only transferred(S600).
摘要翻译：目的：提供数据生成和发送方法，以通过减少在上位处理器和链路线路设备之间传送的信号数据的量来改善上位处理器的性能，而不需要修改硬件。构成：描述了包括传输算法的数据产生和传输方法。传输算法包括初始化用于数据传输的程序（S100）。通过将先前的信号数据与上位处理器中的当前信号数据进行比较来生成16字节的数据（S200）。通过将16字节数据与设置的字节数进行比较来生成2字节数据（S300）。在上位处理器（S400）传送2字节数据后，根据传送的2字节数据（S500）的比较判断是否传送了16字节数据。如果2字节数据与设定值相同，则进入步骤（S500）。如果2字节的数据与设定值不相同，则仅传送变化的信号数据（S600）。

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