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    • 2. 发明公开
    • 반도체 장치 및 반도체 장치의 제조 방법
    • 半导体器件及其制造方法
    • KR1020080034398A
    • 2008-04-21
    • KR1020070103029
    • 2007-10-12
    • 소니 주식회사
    • 다이가오리쓰카모토마사노리나카타마사시오시야마이타루
    • H01L21/336H01L29/78H01L21/28
    • H01L21/823842H01L21/76895H01L21/823871H01L29/66545
    • A semiconductor device and a method for manufacturing the same are provided to restrain electric resistance increase of a gate electrode by forming gate electrodes which comprise different kinds of insulation gate MISFETs out of conductive materials having a desired work function value. A semiconductor device comprises an N-channel MISFET and a P-channel MISFET. A first insulating layer and a second insulating layer are formed on a substrate. Contact plugs for gate electrode(44A,44B) penetrate the second insulating layer, and are connected with each gate electrode of the MISFETs. Contact plugs for source/drain(45A,45B) penetrate the insulating layers, and are connected with each source/drain region of the MISFETs. Each gate electrode is buried into an opening for forming gate electrode which is formed on the first insulating layer. A gate electrode of the N-channel MISFET(32A) comprises a lower surface and a side surface made of a first conductive material. The gate electrode of the P-channel MISFET(32B) comprises the lower surface and the side surface made of a second conductive material which is different from the first conductive material. Conductive protection layers are formed on the upper surfaces of each gate electrode. The contact plug which is connected to the gate electrode of the N-channel MISFET is connected to the upper surface thereof through the protection layer, and the contact plug which is connected to the gate electrode of the P-channel MISFET is connected to the upper surface thereof through the protection layer.
    • 提供半导体器件及其制造方法,以通过从具有期望功函数值的导电材料中形成包括不同种类的绝缘栅极MISFET的栅电极来抑制栅电极的电阻增加。 半导体器件包括N沟道MISFET和P沟道MISFET。 在基板上形成第一绝缘层和第二绝缘层。 栅电极(44A,44B)的接触插塞穿透第二绝缘层,并与MISFET的每个栅电极连接。 用于源极/漏极(45A,45B)的接触插塞穿透绝缘层,并与MISFET的每个源极/漏极区域连接。 每个栅电极被埋入用于形成在第一绝缘层上的栅电极的开口。 N沟道MISFET(32A)的栅电极包括下表面和由第一导电材料制成的侧表面。 P沟道MISFET(32B)的栅电极包括由不同于第一导电材料的第二导电材料制成的下表面和侧表面。 导电保护层形成在每个栅电极的上表面上。 连接到N沟道MISFET的栅电极的接触插塞通过保护层连接到其上表面,并且连接到P沟道MISFET的栅电极的接触插塞连接到上部 其表面通过保护层。