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1. 发明公开

KR1020090067290A 반도체 소자의 게이트 전극 및 그 형성 방법. 无效
标题翻译：形成门电极的方法
公开(公告)号：KR1020090067290A
公开(公告)日：2009-06-25
申请号：KR1020070134869
申请日：2007-12-21
申请人： 삼성전자주식회사
发明人： 장대영
IPC分类号： H01L29/78
CPC分类号： H01L27/10823 , H01L21/76224 , H01L27/10876 , H01L29/66795 , H01L29/785
摘要： A gate electrode of a semiconductor device and a forming method thereof are provided to increase a manufacturing yield of the semiconductor device by reducing defects due to disconnection of a gate electrode in a second active pattern part. A gate electrode of a semiconductor device includes a substrate, an isolation layer pattern, and a conductive layer pattern(122). The substrate includes a first active pattern(106a) and a second active pattern(108a). The first active pattern has a first sidewall slope. The second active pattern has a second sidewall slope. The second sidewall slope is lower than the first sidewall slope. The substrate includes a first recess. The first recess is generated at a gate electrode forming part in the first and second active patterns. The first recess includes an active fence protruded from a bottom surface thereof. The isolation layer pattern includes a second recess. The second recess is formed between the first and second active patterns. The second recess is formed at the gate electrode forming part in order to be connected with the first recess. A conductive layer pattern is formed in the inside of the first and second recesses. The conductive layer pattern has the same pitch in the first and second active patterns.
摘要翻译：提供半导体器件的栅电极及其形成方法，以通过减少由于第二有源图形部分中的栅电极的断开而导致的缺陷来提高半导体器件的制造成品率。半导体器件的栅电极包括衬底，隔离层图案和导电层图案（122）。衬底包括第一有源图案（106a）和第二有源图案（108a）。第一活动图案具有第一侧壁倾斜。第二活动图案具有第二侧壁斜面。第二侧壁斜率低于第一侧壁斜率。基板包括第一凹部。在第一和第二活性图案中的栅电极形成部分产生第一凹槽。第一凹部包括从底面突出的活动围栏。隔离层图案包括第二凹部。第二凹部形成在第一和第二活性图案之间。第二凹部形成在栅电极形成部分处以便与第一凹部连接。导电层图案形成在第一和第二凹部的内部。导电层图案在第一和第二活性图案中具有相同的间距。

2. 发明公开

KR1020090110170A 반도체 소자 및 그의 제조 방법 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：KR1020090110170A
公开(公告)日：2009-10-21
申请号：KR1020080035817
申请日：2008-04-17
申请人： 삼성전자주식회사
发明人： 유호인 , 김봉수 , 김대익 , 장대영 , 이호준
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L29/66621
摘要： PURPOSE: A semiconductor device and a manufacturing method for improving the reliability of an element are provided to equip a buffer layer for reducing stress between a capping layer and a semiconductor substrate. CONSTITUTION: A semiconductor device includes a semiconductor substrate, an impurity domain frame, a gate electrode(110), a gate insulating layer(160), a capping layer(130), and a buffer layer(150). A trench is created on the semiconductor substrate. The impurity domain frame is formed on both sides of the semiconductor substrate of the trench. The gate electrode is reclaimed inside the trench. The gate electrode is overlapped in the impurity region. The capping layer is formed on the top of the gate electrode. The buffer layer is formed between the capping layer and the impurity region.
摘要翻译：目的：提供一种用于提高元件的可靠性的半导体器件和制造方法，以设置用于减小覆盖层和半导体衬底之间的应力的缓冲层。构成：半导体器件包括半导体衬底，杂质域框架，栅电极（110），栅极绝缘层（160），覆盖层（130）和缓冲层（150）。在半导体衬底上形成沟槽。杂质畴框架形成在沟槽的半导体衬底的两侧。在沟槽内回填栅电极。栅电极在杂质区域重叠。覆盖层形成在栅电极的顶部。缓冲层形成在封盖层和杂质区之间。

3. 发明授权

KR101823532B1 Ｘ선 디텍터 장치 및 Ｘ선 디텍터 장치의 동작 방법 有权
标题翻译： X射线探测器装置和X射线探测器装置的操作方法
公开(公告)号：KR101823532B1
公开(公告)日：2018-01-30
申请号：KR1020160009400
申请日：2016-01-26
申请人： 삼성전자주식회사
发明人： 박성규 , 장대영 , 홍기조 , 김희철 , 조정근
IPC分类号： G01T1/24 , G01T7/12 , G01T1/167
CPC分类号： A61B6/4208 , A61B6/03 , A61B6/032 , A61B6/4266 , A61B6/54 , A61B6/56 , G01T1/244
摘要： 본개시의일 실시예에는, X선단층촬영을진행하는동안에 X선디텍터모듈에공급되는전원을제어하는 X선디텍터장치및 X선디텍터장치의동작방법을제공한다. 본개시의일 실시예는, 방열구조를갖는 X선디텍터모듈을포함하는 X선디텍터장치를제공한다.
摘要翻译：本公开的一个实施例提供了一种用于在X射线断层摄影期间控制提供给X射线探测器模块的功率的X射线探测器装置和X射线探测器装置的操作方法。本公开的一个实施例提供了一种包括具有散热结构的X射线检测器模块的X射线检测器装置。

4. 发明公开

KR1020170089243A Ｘ선 디텍터 장치 및 Ｘ선 디텍터 장치의 동작 방법 审中-实审
公开(公告)号：KR1020170089243A
公开(公告)日：2017-08-03
申请号：KR1020160009400
申请日：2016-01-26
申请人： 삼성전자주식회사
发明人： 박성규 , 장대영 , 홍기조 , 김희철 , 조정근
IPC分类号： G01T1/24 , G01T7/12 , G01T1/167
CPC分类号： A61B6/4208 , A61B6/025 , A61B6/03 , A61B6/4266 , A61B6/54 , A61B6/56
摘要： 본개시의일 실시예에는, X선단층촬영을진행하는동안에 X선디텍터모듈에공급되는전원을제어하는 X선디텍터장치및 X선디텍터장치의동작방법을제공한다. 본개시의일 실시예는, 방열구조를갖는 X선디텍터모듈을포함하는 X선디텍터장치를제공한다.

5. 发明授权

KR101535222B1 반도체 소자 및 그의 제조 방법 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：KR101535222B1
公开(公告)日：2015-07-08
申请号：KR1020080035817
申请日：2008-04-17
申请人： 삼성전자주식회사
发明人： 유호인 , 김봉수 , 김대익 , 장대영 , 이호준
IPC分类号： H01L29/78
CPC分类号： H01L29/4236 , H01L29/66621
摘要： 본발명은반도체소자및 그의제조방법에관한것으로서, 더욱구체적으로는트렌치가형성된반도체기판; 상기트렌치의양 쪽반도체기판에형성된불순물영역들; 상기트렌치의내부에매립되고상기불순물영역과중첩되는게이트전극; 상기게이트전극과상기트렌치표면사이에형성된게이트절연막; 상기게이트절연막의상부에형성된캡핑층; 및상기캡핑층과상기불순물영역사이에형성된버퍼(buffer)막을포함하는반도체소자를제공한다. 본발명의반도체소자및 그의제조방법을이용하면, 캡핑막과반도체기판사이의스트레스를완화시킬수 있다.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及一种半导体器件及其制造方法，更具体地，涉及一种其中形成有沟槽的半导体器件; 在沟槽的两个半导体衬底上形成的杂质区域; 埋入沟槽中并与杂质区重叠的栅电极; 在栅电极和沟槽表面之间形成的栅极绝缘膜; 形成在栅极绝缘层上的覆盖层; 并且在覆盖层和杂质区域之间形成缓冲膜。通过使用本发明的半导体器件和制造方法，可以减轻封盖膜和半导体衬底之间的应力。

6. 发明授权

KR100876079B1 배선 구조물 형성 방법 有权
标题翻译：形成线结构的方法
公开(公告)号：KR100876079B1
公开(公告)日：2008-12-26
申请号：KR1020070063016
申请日：2007-06-26
申请人： 삼성전자주식회사
发明人： 이호준 , 김용일 , 김봉수 , 장대영 , 조우정
IPC分类号： H01L21/027 , H01L21/28
CPC分类号： H01L27/105 , H01L23/535 , H01L2924/0002 , H01L21/0274 , H01L21/28008 , H01L2924/00
摘要： The method for forming the wiring structure is provided to improve the reliability of the semiconductor device by applying voltage to actives through the contact which can be changed according to the location of the silicon fence. The method for forming the wiring structure comprises as follows. A step is for forming the first active(104a) having the first side wall having the positive slope and the second active(104b) arranged in the first direction which is depart from first active in the semiconductor substrate. A step is for forming the element isolation film(106) by burying the gap between the first and second actives on the semiconductor substrate. The step is for forming the mask pattern having the opening which is extended in the first direction on the first active, and second actives and element isolation film and exposes the first lateral wall. A step is for forming the groove in the first direction by etching the element isolation film using the mask pattern as the etching mask and for changing the fence(44b) having a higher height than the groove. A step is for forming the wiring(110) which buries the groove. A step is for forming on the wiring the contact(112) to locate in the direction of the second active.
摘要翻译：提供了用于形成布线结构的方法，以通过通过可以根据硅栅栏的位置改变的接触向活性物质施加电压来提高半导体器件的可靠性。形成布线结构的方法包括如下。步骤是用于形成具有正斜率的第一侧壁的第一有源（104a）和在半导体衬底中离开第一有源的第一方向排列的第二有源（104b）。通过掩埋半导体衬底上的第一和第二活性物之间的间隙来形成元件隔离膜（106）的步骤。该步骤用于形成具有在第一活性物上沿第一方向延伸的开口的掩模图案，以及第二活性物质和元素隔离膜并暴露第一侧壁。通过使用掩模图案作为蚀刻掩模蚀刻元件隔离膜并且改变具有比槽高的高度的栅栏（44b），步骤是通过蚀刻元件隔离膜来形成第一方向的沟槽。形成埋设槽的布线（110）的步骤。一个步骤是在触点（112）的布线上形成在第二活动的方向上定位的步骤。

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