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71. 发明公开

KR1020030002432A 클럭 동기 장치 失效
标题翻译：时钟同步装置
公开(公告)号：KR1020030002432A
公开(公告)日：2003-01-09
申请号：KR1020010038031
申请日：2001-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 김세준 , 홍상훈
IPC分类号： H03L7/00
CPC分类号： H03L7/089 , H03L7/0812 , H04L7/0037
摘要： PURPOSE: A clock synchronizing device is provided, which improves a jitter characteristics even though a low frequency clock signal is inputted, by making a constant phase resolution. CONSTITUTION: A phase detection unit(10) compares phases of an external clock signal and an internal clock signal, and a code generation unit(20,30) generates a code value of N bit according to an output signal of the phase detection unit. A digital/analog conversion unit outputs a voltage corresponding to the code value of the N bit of the code generation unit. A level detection unit(70) compares a reference voltage with the voltage being output by the digital/analog conversion unit, and then outputs a control signal controlling an output voltage value of the digital/analog conversion unit according to the comparison result. And a clock synchronization control unit outputs an internal clock signal by delaying the external clock signal according to a voltage generated by the digital/analog conversion unit. The digital/analog conversion unit comprises a main digital/analog conversion unit(50) outputting a voltage corresponding to upper N-M bit of the code value of the N bit, and a sub digital/analog conversion unit(60) outputting a voltage corresponding to a lower M bit by being enabled according to a control signal of the level detection unit.
摘要翻译：目的：提供一种时钟同步装置，即使输入低频时钟信号，也能通过使相位分辨率保持恒定，从而改善抖动特性。构成：相位检测单元（10）比较外部时钟信号和内部时钟信号的相位，代码生成单元（20,30）根据相位检测单元的输出信号生成N位的代码值。数字/模拟转换单元输出与代码生成单元的N位的代码值对应的电压。电平检测单元（70）将参考电压与由数字/模拟转换单元输出的电压进行比较，然后根据比较结果输出控制数字/模拟转换单元的输出电压值的控制信号。并且时钟同步控制单元通过根据由数字/模拟转换单元产生的电压延迟外部时钟信号来输出内部时钟信号。数字/模拟转换单元包括：主数字/模拟转换单元（50），输出对应于N位代码值的上NM位的电压;以及副数字/模拟转换单元（60），输出对应于通过根据电平检测单元的控制信号使能下位M位。

72. 发明公开

KR1020030002419A 반도체 메모리 장치 및 그 테스트 방법 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：KR1020030002419A
公开(公告)日：2003-01-09
申请号：KR1020010038018
申请日：2001-06-29
申请人： 에스케이하이닉스 주식회사
发明人： 홍상훈 , 김시홍
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G11C11/401 , G11C29/14 , G11C29/50 , G11C29/50012
摘要： PURPOSE: A semiconductor memory device and a test method thereof are provided, which detects a worst operation condition without an operation error of the whole memory cell array and cells and then reduces a current consumption of the memory device by operating the memory device the optimized operation condition. CONSTITUTION: A memory cell array(2) includes a plurality of memory cells, and memory cells repaired by being judged as fail through the first test among the plurality of memory cells, and a test cell(1) repaired by being judged as a memory cell easy to fail among the memory cells judged as pass. A test unit(3) performs the second test using a fixed operation condition as to the test cell, and repeats the second test or outputs the operation condition controlled finally by controlling the operation condition as to the test cell according to the result of the second test. And a driver unit(4) drives the memory cell array using the operation condition being output from the test unit.
摘要翻译：目的：提供一种半导体存储器件及其测试方法，其在没有整个存储单元阵列和单元的操作错误的情况下检测最差的操作条件，然后通过操作存储器件优化的操作来降低存储器件的电流消耗条件。构成：存储单元阵列（2）包括多个存储单元，以及通过在多个存储单元中的第一测试被判定为故障而修复的存储单元，以及通过被判断为存储器来修复的测试单元（1）记忆细胞中的细胞容易失败，判定为通过。测试单元（3）使用关于测试单元的固定操作条件进行第二测试，并且重复第二测试或输出最终通过根据第二测试单元的结果控制测试单元的操作条件来控制的操作条件测试。并且驱动器单元（4）使用从测试单元输出的操作条件驱动存储单元阵列。

73. 发明公开

KR1020020044200A 내부전압 발생회로 失效
标题翻译：内部电压发生电路
公开(公告)号：KR1020020044200A
公开(公告)日：2002-06-15
申请号：KR1020000073179
申请日：2000-12-05
申请人： 에스케이하이닉스 주식회사
发明人： 김시홍 , 홍상훈
IPC分类号： G11C5/14
CPC分类号： G05F3/247 , G05F1/465
摘要： PURPOSE: An internal voltage generating circuit is provided to constantly keep a defined voltage level by supplying a first current providing path from an outer power source to an internal voltage and a second current providing path from the internal voltage to an outer ground. CONSTITUTION: An internal voltage generating circuit(200) comprises a comparison part(210) comparing first reference voltage(Vref1) and second reference voltage(Vref2) with internal voltage(Vint). A driving part(220) controls internal voltage by receiving the output signal of the comparator part(210). When internal voltage(Vint) is lower than the first and second reference voltages(Vref1,Vref2), the driving part(220) increases the internal voltage level by flowing current from an outer power source to the internal voltage(Vint). In opposite case, the driving part(220) decreases the internal voltage level by flowing current from the internal voltage(Vint) to an outer ground.
摘要翻译：目的：提供内部电压发生电路以通过从外部电源提供第一电流提供路径到内部电压以及从内部电压到外部地面的第二电流提供路径来恒定地保持限定的电压电平。构成：内部电压产生电路（200）包括将第一参考电压（Vref1）和第二参考电压（Vref2）与内部电压（Vint）进行比较的比较部分（210）。驱动部分（220）通过接收比较器部分（210）的输出信号来控制内部电压。当内部电压（Vint）低于第一和第二参考电压（Vref1，Vref2）时，驱动部分（220）通过将电流从外部电源流动到内部电压（Vint）来增加内部电压电平。在相反的情况下，驱动部分（220）通过使电流从内部电压（Vint）流动到外部地面来降低内部电压电平。

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