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    • 31. 发明公开
    • 반도체 패키지 및 그 제조 방법
    • 半导体封装及其制造方法
    • KR1020140064522A
    • 2014-05-28
    • KR1020120131940
    • 2012-11-20
    • 삼성전자주식회사
    • 김원근박상욱
    • H01L23/48
    • H01L21/561H01L21/76898H01L23/525H01L23/5329H01L24/94H01L24/97H01L25/0657H01L25/50H01L2224/0401H01L2224/0557H01L2224/06181H01L2224/16145H01L2224/16146H01L2224/1703H01L2224/17181H01L2224/32145H01L2224/73204H01L2224/92125H01L2224/94H01L2224/97H01L2225/06513H01L2225/06541H01L2225/06565H01L2225/06568H01L2924/00014H01L2924/12042H01L2924/1306H01L2924/13091H01L2924/1461H01L2924/15311H01L2924/181H01L2924/18161H01L2924/00012H01L2924/00H01L2224/05552H01L2224/81H01L2224/83
    • Disclosed are a semiconductor packet capable of decreasing the whole height of a semiconductor packet and a manufacturing method thereof. The semiconductor package of the present invention comprises a first semiconductor substrate having a first active surface and a first non-active surface facing each other; a first semiconductor element formed on the first active surface of the first semiconductor substrate; a first semiconductor chip including a pad electrically connected to a first penetration electrode or a first semiconductor element and the first penetration electrode passing through the first semiconductor substrate; and at least one print circuit layer including a resin layer having an upper and lower surface facing each other, a via electrode electrically connected to the first semiconductor chip while passing through the resin layer, and a wiring layer formed on the upper surface of the resin layer and connected to the via electrode. The present invention also includes a print circuit structure formed on the first semiconductor chip for the lower surface of the resin layer to face the first active surface of the first semiconductor substrate; and an external connection element electrically connected to the via electrode and wiring layer, attached on a surface facing the first semiconductor chip of the print circuit structure and the second semiconductor chip electrically connected to the first passing electrode, and attached on the first semiconductor chip to face the first non-active surface of the first semiconductor surface.
    • 公开了能够降低半导体封装的整体高度的半导体封装及其制造方法。 本发明的半导体封装包括具有彼此面对的第一有源表面和第一非有效表面的第一半导体衬底; 形成在所述第一半导体衬底的所述第一有源表面上的第一半导体元件; 第一半导体芯片,包括电连接到第一穿透电极或第一半导体元件的焊盘,以及穿过第一半导体衬底的第一穿透电极; 以及包括具有彼此面对的上表面和下表面的树脂层的至少一个印刷电路层,在通过树脂层的同时电连接到第一半导体芯片的通孔电极以及形成在树脂的上表面上的布线层 层并连接到通孔电极。 本发明还包括形成在第一半导体芯片上用于树脂层的下表面以与第一半导体衬底的第一有源表面相对的印刷电路结构; 以及外部连接元件,其电连接到所述通孔电极和布线层,所述外部连接元件安装在与所述印刷电路结构的所述第一半导体芯片相对的表面上,所述第二半导体芯片与所述第一通过电极电连接,并且附接到所述第一半导体芯片上 面对第一半导体表面的第一非活性表面。
    • 33. 发明公开
    • 칩 뒷면 보호 필름, 그 제조 방법 및 이를 이용한 반도체패키지의 제조 방법
    • 背面保护膜,其形成方法及使用其制造半导体封装的方法
    • KR1020090061996A
    • 2009-06-17
    • KR1020070129055
    • 2007-12-12
    • 삼성전자주식회사
    • 김원근이용관
    • H01L21/48
    • H01L21/6835H01L21/561H01L21/6836H01L21/78H01L23/3114H01L2221/68327H01L2221/68336H01L2224/16
    • A method of manufacturing the backside protection film is provided to cover a semiconductor chip without generating a damage of the semiconductor chip. A back side protection film(10) has the second coating film(32b) and the first coating film(32a) on the release film. The first coating film and the second coating film are formed with the material of protecting the surface of the semiconductor chip. The release film is adhered on the second coating film and can be easily separated. In the first stage of the film manufacture, the first coating film is separated from the first release film. The first coating film is adhered on the second coating film. The release film is formed by coating the second material on the first substance film. The first coating film is formed by changing the first adhesion solution to C-stage state. The second coating film is formed by changing the second adhesion solution to B-stage state.
    • 提供制造背面保护膜的方法来覆盖半导体芯片而不产生半导体芯片的损坏。 背面保护膜(10)在剥离膜上具有第二涂膜(32b)和第一涂膜(32a)。 第一涂膜和第二涂膜由保护半导体芯片的表面的材料形成。 剥离膜粘附在第二涂膜上并且可以容易地分离。 在薄膜制造的第一阶段,第一涂膜与第一脱模膜分离。 第一涂膜粘附在第二涂膜上。 通过将第二材料涂覆在第一物质膜上而形成剥离膜。 通过将第一粘附溶液改变为C阶段状态来形成第一涂膜。 通过将第二粘附溶液改变为B阶状态来形成第二涂膜。
    • 34. 发明公开
    • 개선된 배기구조를 갖는 반도체제조설비용 진공설비
    • 具有改进排气结构的半导体制造设备的真空设备
    • KR1020030047005A
    • 2003-06-18
    • KR1020010077371
    • 2001-12-07
    • 삼성전자주식회사
    • 김원근
    • H01L21/02
    • PURPOSE: A vacuum equipment for a semiconductor manufacturing equipment having an improved exhaust structure is provided to be capable of preventing oil from filling up an exhaust line and recycling the oil by using an oil drain part. CONSTITUTION: A vacuum equipment is provided with a vacuum chamber(11) for carrying out predetermined processes, a vacuum pump(15) connected through a vacuum line to the vacuum chamber(11) for forming a vacuum state in the vacuum chamber(11), an exhaust duct(17) for exhausting the exhaust gas supplied from the vacuum pump(15), and an oil drain part(20) installed on an exhaust line(13) between the vacuum pump(15) and the exhaust duct(17) for draining the oil exhausted from the vacuum pump(15). At this time, the oil is drained by using a switching part and a spring part of the oil drain part.
    • 目的:提供一种具有改进的排气结构的半导体制造设备的真空设备,以能够防止油通过排油部分填充排气管线并再循环油。 构成:真空设备设有用于执行预定过程的真空室(11),通过真空管线连接到真空室(11)的真空泵(15),用于在真空室(11)中形成真空状态, ,用于排出从真空泵(15)供给的排气的排气管道(17)和安装在真空泵(15)和排气管道(17)之间的排气管(13)上的排油部(20) ),用于排出从真空泵(15)排出的油。 此时,通过使用排油部的切换部和弹簧部排出油。
    • 35. 发明公开
    • 자동 압력 조절장치
    • 自动压力控制器
    • KR1020000013625A
    • 2000-03-06
    • KR1019980032593
    • 1998-08-11
    • 삼성전자주식회사
    • 김원근
    • H01L21/20
    • PURPOSE: The pressure of the chamber from raising higher than atmospheric pressure while producing semiconductor manufacture, this device is to prevent a gate opening for reducing pressure in supplying gas for fuzzy in the chamber and to prevent a particle from scattering due to turbulent occurrence of a gate in the opening to lower pressure. CONSTITUTION: This device comprises of a branch pipe that is separated from a gas applying pipe to the chamber and a check valve in the branch pipe that controls the pressure that affects the chamber. And a part of the check valve is connected to atmospheric pressure.
    • 目的:在制造半导体制造过程中,室内压力升高高于大气压,该装置是为了防止在室内提供气体供应气体以减少压力的闸门开口,并防止颗粒由于湍流发生而飞散 门口开口压力较低。 构成:该装置包括从气体施加管分离到室的分支管和分支管中的止回阀,其控制影响室的压力。 止回阀的一部分与大气压连接。
    • 36. 发明公开
    • 건식 식각 장치의 음극판
    • 干蚀刻设备的阴极板
    • KR1019990016568A
    • 1999-03-15
    • KR1019970039144
    • 1997-08-18
    • 삼성전자주식회사
    • 김원근
    • H01L21/306
    • 본 발명은 건식 식각 장치의 반응실(Reaction chamber) 내에서 웨이퍼가 놓여지는 음극판(Cathode)에 관한 것으로, 더욱 구체적으로는 식각 공정이 실시됨에 따라 폴리머(Polymer)와 같은 식각 잔여물이 웨이퍼가 놓여지는 음극판의 접촉면 위에 증착되는 것을 방지할 수 있는 건식 식각 장치의 음극판에 관한 것이며, 이를 위하여 음극판의 접촉면을 웨이퍼의 형태와 같게 형성하고 접촉면을 웨이퍼의 직경보다 작은 직경으로 형성하여 웨이퍼가 놓여질 때 음극판의 접촉면 전체를 덮어씌울 수 있는 구조를 개시하고, 이러한 구조를 통하여 접촉면 위에 식각 잔여물이 증착되지 않게 함으로써 종래 음극판 위에 증착된 식각 잔여물이 웨이퍼 표면을 손상시키는 것을 방지할 수 있으며, 결과적으로 장치를 가동함에 있어서 장치의 정비주기를 연장하여 공정의 효율� � 향상할 수 있다.
    • 37. 发明授权
    • 멀티채널 박막트랜지스터
    • 多通道TFT
    • KR1019950009802B1
    • 1995-08-28
    • KR1019920005291
    • 1992-03-30
    • 삼성전자주식회사
    • 한정인김철수김원근
    • H01L29/786
    • The multichannel thin film transistor includes a lower gate electrode vertically extended on a substrate, a plurality of sub semiconductor layers having a channel region superposed on the lower gate electrode and ohmic contact region extended from both side of the channel region, the sub semiconductor layers being separated from one another and horizontally extended on the lower gate electrode having a gate insulating layer therebetween, source and drain electrodes which comes into contact with the sub semiconductor layers and ohmic contact region, and a upper gate electrode vertically extended on a gate insulating layer, to cover the channel region.
    • 多通道薄膜晶体管包括在基板上垂直延伸的下栅电极,多个次半导体层,其具有重叠在下栅电极上的沟道区和从沟道区的两侧延伸的欧姆接触区,子半导体层为 彼此分离并在其上具有栅极绝缘层的下部栅电极上水平延伸,与次半导体层和欧姆接触区域接触的源极和漏极以及在栅极绝缘层上垂直延伸的上部栅电极, 覆盖通道区域。