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21. 发明授权

KR100665852B1 반도체 소자의 제조방법 失效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100665852B1
公开(公告)日：2007-01-09
申请号：KR1020050070854
申请日：2005-08-03
申请人： 삼성전자주식회사
发明人： 곽병호 , 장범수
IPC分类号： H01L21/28 , H01L21/24
CPC分类号： H01L21/28531
摘要： A method for manufacturing a semiconductor device is provided to maximize productivity by preventing generation of a cavity on a fourth conductive layer between a first conductive layer and a second conductive layer by using a metal silicide layer. A first conductive layer(112) is formed on a semiconductor substrate(110). A first interlayer dielectric(114) is formed on the first conductive layer. A polysilicon layer is formed on the first interlayer dielectric. A second interlayer dielectric(118) is formed on the polysilicon layer. A mask layer is formed on the second interlayer dielectric. A contact hole(120) is formed to expose the first conductive layer. A recess(128) is formed between the first and second interlayer dielectrics. A third conductive layer is formed on a bottom or a sidewall of the contact hole. A metal silicide layer is formed within the contact hole in order to bury the recess. A fourth conductive layer is formed within the contact hole in order to bury the contact hole.
摘要翻译：提供了一种用于制造半导体器件的方法，以通过使用金属硅化物层防止在第一导电层和第二导电层之间的第四导电层上产生腔来最大化生产率。第一导电层（112）形成在半导体衬底（110）上。第一层间电介质（114）形成在第一导电层上。在第一层间电介质上形成多晶硅层。在多晶硅层上形成第二层间电介质（118）。在第二层间电介质上形成掩模层。形成接触孔（120）以露出第一导电层。在第一和第二层间电介质之间形成凹部（128）。第三导电层形成在接触孔的底部或侧壁上。在接触孔内形成金属硅化物层以便埋入凹部。为了埋入接触孔，在接触孔内形成第四导电层。

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