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    • 21. 发明公开
    • 셀 설계 정보를 전송하는 이동통신단말기, 시스템 및 방법
    • 移动电信设备,用于发送小区计划信息的系统和方法
    • KR1020060126049A
    • 2006-12-07
    • KR1020050047641
    • 2005-06-03
    • 엘지전자 주식회사
    • 김인철
    • H04B7/26H04B1/40H04W88/02H04W4/02
    • H04W16/24H04W4/02H04W64/00H04W88/02
    • A mobile communication terminal, and a system and method for transmitting cell planning information are provided to calculate location information of the mobile communication terminal and broadcasting reception information corresponding to the location information by using the mobile communication terminal and transmit the calculated location information and broadcasting reception information to a database unit which manages cell planning, thereby providing information useful for the cell planning. A location calculating unit(110) calculates location information of a mobile communication terminal(100). An information detecting unit(120) detects broadcasting reception information in accordance with the location information. A control unit(130) determines whether to transmit the location information and the broadcasting reception information to a database unit(190) or not. An information transmitting unit(140) transmits the location information and the broadcasting reception information to the database unit(190) according to a control signal of the control unit(130).
    • 提供一种移动通信终端,以及用于发送小区规划信息的系统和方法,通过使用移动通信终端来计算移动通信终端的位置信息和对应于该位置信息的广播接收信息,并发送所计算的位置信息和广播接收 信息到管理小区规划的数据库单元,从而提供对小区规划有用的信息。 位置计算单元(110)计算移动通信终端(100)的位置信息。 信息检测单元(120)根据位置信息检测广播接收信息。 控制单元(130)确定是否将位置信息和广播接收信息发送到数据库单元(190)。 信息发送单元(140)根据控制单元(130)的控制信号将位置信息和广播接收信息发送到数据库单元(190)。
    • 22. 发明授权
    • 교환기에서 프로세서간 메모리 동일성 검증 방법 및 그 장치
    • 교환기에서프로세서간메모리동일성검증방법및그장치
    • KR100398731B1
    • 2003-09-19
    • KR1019990062789
    • 1999-12-27
    • 엘지전자 주식회사
    • 김인철
    • H04M3/22
    • PURPOSE: A method and a device for verifying an inter-processor memory identity in an exchange are provided to use a PCI(Peripheral Component Interconnect) bus and a PCI-processor bus bridge without using a complicated logic and address/data FIFO(First In First Out) logic, so as to simplify a logic and reduce procedure. CONSTITUTION: A PCI(Peripheral Component Interconnect) bridge/memory controller(2) of an active processor loads a standby processor memory read address generated by a CPU(1) of the active processor to a PCI bus. A PCI-processor bus bridge(7) of the active processor converts the address loaded on the PCI bus to a duplexing channel address, to be loaded on a duplexing channel. A PCI-processor bus bridge(7) of the standby processor receives the address loaded on the duplexing channel, to convert the address through reverse conversion for the conversion of the PCI-processor bus bridge(7) of the active processor to be loaded on the PCI bus. A PCI bridge/memory controller(2) of the standby processor receives the address loaded on the PCI bus to be converted into a memory access address, and accesses a memory and receives data to load the data on the PCI bus. The PCI-processor bus bridge(7) of the standby processor converts the data loaded on the PCI bus, to be loaded on the duplexing channel. The PCI-processor bus bridge(7) of the active processor converts the data loaded on the duplexing channel, to be loaded on the PCI bus. And a PCI bridge/memory controller(2) of the active processor delivers the data loaded on the PCI bus to the CPU(1).
    • 目的:提供一种用于验证交换机中的处理器间存储器身份的方法和设备,以使用PCI(外围组件互连)总线和PCI处理器总线桥而不使用复杂的逻辑和地址/数据FIFO(First In 先出)逻辑,以简化逻辑并减少过程。 构成:活动处理器的PCI(外设部件互连)桥接器/存储器控制器(2)将由活动处理器的CPU(1)产生的备用处理器存储器读地址加载到PCI总线。 活动处理器的PCI处理器总线桥(7)将加载在PCI总线上的地址转换为双工信道地址,以加载到双工信道上。 备用处理器的PCI处理器总线桥接器(7)接收加载在双工信道上的地址,通过反向转换来转换地址,以便转换要加载的活动处理器的PCI处理器总线桥接器(7) PCI总线。 备用处理器的PCI桥/存储器控制器(2)接收加载在PCI总线上的地址以转换成存储器访问地址,并访问存储器并接收数据以将数据加载到PCI总线上。 备用处理器的PCI处理器总线桥(7)转换加载在PCI总线上的数据,以加载到双工信道上。 活动处理器的PCI处理器总线桥(7)将加载在双工信道上的数据转换成加载在PCI总线上。 并且活动处理器的PCI桥/内存控制器(2)将加载在PCI总线上的数据传送到CPU(1)。
    • 23. 发明公开
    • FIR 필터의 CSD 계수 산출방법
    • 在有限冲突响应过滤器中计算CANONIC签名数字系数的方法
    • KR1020090103144A
    • 2009-10-01
    • KR1020080028547
    • 2008-03-27
    • 엘지전자 주식회사
    • 김인철이희섭김성천김기철김홍득
    • H03H17/00
    • H03H17/0227H03H17/0211H03H17/0238H03H17/0657
    • PURPOSE: A method for calculating the CSD coefficient of an FIR filter is provided to calculate the CSD coefficient by using an MILP(Mixed Integer Linear Programming) algorithm. CONSTITUTION: A method for calculating the CSD coefficient of an FIR filter comprises the following steps of: setting up the length N, resolution B and the number of bits Z of a designed FIR(Finite Impulse Response) filter(S400); setting up a variable i for increasing the length N and a variable j for increasing the resolution B into zero(S402); and calculating the CSD(Canonic Signed Digit) coefficient and the size of a ripple by executing MILP(Mixed Integer Linear Programming) algorithm with N+2i, B+j and Z(S404).
    • 目的:提供一种用于计算FIR滤波器的CSD系数的方法,以通过使用MILP(混合整数线性规划)算法来计算CSD系数。 构成:用于计算FIR滤波器的CSD系数的方法包括以下步骤:设置设计的FIR(有限脉冲响应)滤波器的长度N,分辨率B和位数Z(S400); 设置用于增加长度N的变量i和用于将分辨率B增加为零的变量j(S402); 并通过执行N + 2i,B + j和Z(S404)的MILP(混合整数线性规划)算法计算CSD(Canonic Signed Digit)系数和纹波大小。
    • 25. 发明授权
    • 플라즈마 디스플레이 패널의 하판 제조방법
    • 等离子体显示面板的下板制造方法
    • KR100696444B1
    • 2007-03-20
    • KR1020050105856
    • 2005-11-07
    • 엘지전자 주식회사
    • 김용호김인철
    • H01J11/36
    • H01J9/242H01J11/12H01J11/36
    • A lower-board manufacturing method of a plasma display panel is provided to simplify a manufacturing process and reduce a manufacturing cost by forming directly a barrier rib and a lower dielectric layer with a glass powder. A lower barrier rib layer is formed on a substrate(310) including a dielectric layer(330) by using a first glass powder(344a). An upper barrier rib layer is formed on the lower barrier rib layer of the substrate by using a second glass powder. A baking process is performed to bake the lower barrier rib layer and the upper barrier rib layer. A barrier rib is formed by etching the lower barrier rib layer and the upper barrier rib layer.
    • 提供等离子体显示面板的下板制造方法,以通过直接形成具有玻璃粉末的阻挡肋和下介电层来简化制造工艺并降低制造成本。 通过使用第一玻璃粉末(344a)在包括电介质层(330)的基板(310)上形成下阻挡肋层。 通过使用第二玻璃粉末在衬底的下阻挡层上形成上阻挡肋层。 进行烘烤处理以烘烤下阻挡肋层和上阻挡肋层。 通过蚀刻下阻挡肋层和上阻挡肋层形成障壁。
    • 28. 发明授权
    • 교환기에서 디엠 버스 관리 방법
    • 교환기에서디엠버스관리방법
    • KR100439856B1
    • 2004-07-12
    • KR1020010056125
    • 2001-09-12
    • 엘지전자 주식회사
    • 김인철
    • H04M3/22
    • PURPOSE: A method of managing a DM bus in an exchange is provided to supply a self-diagnosable DM bus structure by implementing a loop back function, to decide whether a transceiving function is normal on a bus in real time, thereby having a self-diagnosing function and improving reliability. CONSTITUTION: A master and each slave device are assigned with inherent time slot regions(S1). The master and the slave devices set a loop back path(S2). The master transmits data through a self transmission channel from a master time slot region(S3). Each slave device time slot region receives the transmitted data through self receiving channels according to the set loop back path(S4). The master reads a destination address of the received data, and confirms whether the address is equal to a destination address of the transmitted data(S5). If so, the master compares the transmitted data with loop backed data, and retrieves whether a data error is generated(S6). If so, the master is separated from a DM bus, and performs follow-up measures like initialization(S7).
    • 目的:提供一种管理交换机中的DM总线的方法,通过实现回送功能来提供可自诊断的DM总线结构,以实时判断总线上的收发功能是否正常, 诊断功能和提高可靠性。 构成:主设备和每个从设备被分配固有的时隙区域(S1)。 主设备和从设备设置回路路径(S2)。 主设备通过来自主时隙区域的自传输信道发送数据(S3)。 每个从设备时隙区域根据设置的环回路径通过自己的接收信道接收发送的数据(S4)。 主设备读取接收数据的目的地址,并确认该地址是否等于发送数据的目的地址(S5)。 如果是这样,则主设备比较发送的数据和循环备份数据,并检索是否产生数据错误(S6)。 如果是,则主站与DM总线分离,并执行初始化(S7)等后续措施。
    • 29. 发明授权
    • 교환기의 셀 다중화/역다중화 시스템
    • 교환기의셀다중화/역다중화시스템
    • KR100385133B1
    • 2003-05-22
    • KR1019990058326
    • 1999-12-16
    • 엘지전자 주식회사
    • 이민재김인철
    • H04L12/433
    • PURPOSE: A cell multiplexing and demultiplexing system is provided to minimize data loss when switched owing to node and path abnormality by controlling a data path to be duplicated. CONSTITUTION: A port management assembly(40) compares VPI and VCI values among a header of cell data received from a cell switching module(30) to confirm cell multiplexing/demultiplexing assemblies(50-1 to 50-n) to be transferred. The port management assembly(40) transfers the received cell data to a confirmed cell multiplexing/demultiplexing assembly through an analogous UTOPIA-2 bus. The port management assembly(40) transfers data received from each cell multiplexing/demultiplexing assembly to the cell switching module(30) through the UTOPIA-2 bus. Each cell multiplexing/demultiplexing assembly matches four pairs of processors(60-1 to 60-nm) each processing data.
    • 目的:提供一种信元复用和解复用系统,以通过控制要被复制的数据路径而由于节点和路径异常而切换时最小化数据丢失。 构成:端口管理组件(40)比较从信元交换模块(30)接收的信元数据的头部中的VPI和VCI值,以确认要传送的信元复用/解复用组件(50-1至50-n)。 端口管理组件(40)通过类似的UTOPIA-2总线将接收到的单元数据传送到确认的单元多路复用/多路分解组件。 端口管理组件(40)通过UTOPIA-2总线将从每个单元多路复用/多路分解组件接收到的数据传送到信元交换模块(30)。 每个单元复用/解复用组件匹配每对处理数据的四对处理器(60-1到60-nm)。