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1. 发明专利

JP3522457B2 Vector absolute value calculation circuit 失效
公开(公告)号：JP3522457B2
公开(公告)日：2004-04-26
申请号：JP22940296
申请日：1996-08-13
申请人：株式会社鷹山
发明人：長明周 , 国梁寿 , 山本　　誠 , 一則本橋 , 邦彦鈴木 , 直高取
IPC分类号： G06G7/25 , G06G7/22
CPC分类号： G06G7/22

2. 发明专利

JPH09282402A SIGNAL PROCESSING METHOD AND ITS PROCESSOR 失效
公开(公告)号：JPH09282402A
公开(公告)日：1997-10-31
申请号：JP9449396
申请日：1996-04-16
申请人： FUJITSU LTD
发明人： TAKATSU MOTOMU
IPC分类号： G06G7/14 , G06G7/25
摘要： PROBLEM TO BE SOLVED: To realize addition, subtraction and absolute value arithmetic by a small circuit scale by expressing a signal by the sum or the difference of currents flowing through two signal wires. SOLUTION: The two signal wires are assigned to the signal. When the signal is positive, a current in proportion to the signal value is made to flow through one signal wire but when it is negative, a current in proportion to the absolute value of the signal value is made to flow through the other signal wire. Signal wires SP-1 and SP-2 on the positive side of an input signal are connected and given to an output signal wire SP-3 on the positive side and signal wires SM-1 and SM-2 on the negative side of the input signal are connected and given to an output signal wire SM-3 on the negative side to realize an additional circuit only by connecting wires. For subtraction, addition is executed after inverting a code. For the inversion of the code, the signal wire SP-1 on the positive side and the signal wire SM-1 on the negative side of the input signal are replaced with each other. At the time of connecting the signal wires SP-1 and SM-1, the output of the absolute value is obtained.

3. 发明专利

JPH0814830B2 失效
公开(公告)号：JPH0814830B2
公开(公告)日：1996-02-14
申请号：JP27568786
申请日：1986-11-19
IPC分类号： G06G7/25

4. 发明专利

JPH0522871B2 失效
公开(公告)号：JPH0522871B2
公开(公告)日：1993-03-30
申请号：JP3215884
申请日：1984-02-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KOBAYASHI KATSUMI , NAKADA TADAAKI
IPC分类号： G01R19/02 , G01R19/00 , G01R19/25 , G06G7/12 , G06G7/25 , H03H17/00 , H03H17/02 , H03M1/12

5. 发明专利

JPH0330828B2 失效
公开(公告)号：JPH0330828B2
公开(公告)日：1991-05-01
申请号：JP11010782
申请日：1982-06-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO HARUNORI , SAKANO RYUICHI
IPC分类号： G01R19/22 , G06G7/25 , H02M7/12 , H02M7/21

6. 发明专利

JPH0210467B2 失效
公开(公告)号：JPH0210467B2
公开(公告)日：1990-03-08
申请号：JP11948785
申请日：1985-06-01
申请人： AKAI ELECTRIC
发明人： MATSUNAGA TAKAYUKI
IPC分类号： H03K5/1532 , G06G7/12 , G06G7/25 , H03K6/00

7. 发明专利

JPH0121644B2 失效
公开(公告)号：JPH0121644B2
公开(公告)日：1989-04-21
申请号：JP18417181
申请日：1981-11-16
申请人： MATSUSHITA ELECTRIC WORKS LTD
发明人： KOMODA TAKUYA
IPC分类号： H03H11/52 , G06G7/12 , G06G7/25 , H03G11/08

8. 发明专利

JPS63135006A VOLTAGE LIMITING CIRCUIT 失效
公开(公告)号：JPS63135006A
公开(公告)日：1988-06-07
申请号：JP27981286
申请日：1986-11-26
申请人： OKI ELECTRIC IND CO LTD
发明人： HIRAO YOSHIKAZU
IPC分类号： H03G11/02 , G06F3/05 , G06G7/25
摘要： PURPOSE:To supply an output signal obtained from an operational amplifier to an integrated circuit while the voltage is limited so as not to limit it below a supply voltage of the integrated circuit receiving the output signal by providing a constant voltage drop element receiving an output signal obtained via a current limit resistor and outputting the amplified output signal subjected to voltage limit and a feedback loop supplying the amplified output signal outputted from the constant voltage drop element to an inverted input terminal of the operational amplifier. CONSTITUTION:A 2nd constant voltage drop element 5 connected to other terminal of the current limit resistor 3 decreased a voltage of an output signal outputted via the current limit resistor 3 by a voltage drop having the element 5 and is outputted as an amplified output signal to constitute a part of a feedback loop supplying the amplified output signal to the inverted input terminal of the operational amplifier 2. Thus, the amplified output in matching with the voltage drop of the 2nd constant voltage drop element 5 is outputted at the output of the operational amplifier 2 and the linearity of the operational amplifier 2 applying arithmetic operation and amplification of the inputted analog input signal is ensured.

9. 发明专利

JPS62287380A ABSOLUTE VALUE CONVERTER 失效
公开(公告)号：JPS62287380A
公开(公告)日：1987-12-14
申请号：JP13125186
申请日：1986-06-06
申请人： MITSUBISHI ELECTRIC CORP , RYODEN KOKI ENG KK
发明人： ISHIGURO RYOJI , HARADA TOSHIO
IPC分类号： H03K17/00 , G06G7/25
摘要： PURPOSE:To minimize the influence of the bias current of a differential amplifier as an inversion-noninversion switching circuit upon its output and to obtain high accuracy by switching the differential amplifier which uses an operational amplifier in synchronism with the change of the polarity of an input signal. CONSTITUTION:An analog switch 13a is connected to its upper terminal as shown by a solid line and an analog switch 13b is connected to its right-side terminal, so that the differential amplifier 10 operates as an inverting amplifier whose gain is -1. Further, the analog switch 13a is connected to the lower terminal and the analog switch 13b is connected to the left-side terminal, so that the amplifier becomes a noninverting amplifier whose gain is 1. Namely, the input analog signal V1 is inputted to a polarity detector 14, which outputs an analog switch control signal d0 synchronized with the change of the polarity of the input analog signal V1. Then, the connections of the analog switches 13a and 13b are so controlled with the analog switch control signal d0 that the polarity of the input analog signal V1 is uniform, thereby switching the differential amplifier 10 between the inverting amplifier and noninverting amplifier.

10. 发明专利

JPS62149208A CURRENT CONVERSION CIRCUIT 失效
公开(公告)号：JPS62149208A
公开(公告)日：1987-07-03
申请号：JP28915685
申请日：1985-12-24
申请人： TOSHIBA CORP
发明人： GOMI HIROSHI
IPC分类号： G06G7/25 , H03F3/34 , H03F3/347 , H03G3/10
摘要： PURPOSE:To attain the linear conversion and to make the titled circuit applicable to a gain controller, a limiter circuit or a detection circuit over a wide range by providing plural coupling circuits and plural differential amplifiers comprising m-set of semiconductor coupling circuits. CONSTITUTION:The coupling circuits Fa, Fb consist of transistors (TR) Qa1...Qam and Qb1...Qbm and a bias voltage is applied to bases of the TRs Qa1, Qb1 of the 1st stage from a bias power supply VB1. Moreover, emitters of the TRs Qa1, Qb1 are connected to a base of the TR of the next stage, the TRs are connected similarly sequentially and emitters (output terminals) of the final stage TRs Qam, Qbm are connected to bases of the TRs Qy, Qx constituting the differential amplifier. Further, collectors of the TRs Qa1...Qam and Qb1...Qb(m-1) are connected to a voltage source Vcc. In extracting an output from a point being the connection at least two lines connected to each collector of each differential amplifier TR, the linear conversion is applied and the titled circuit is applicable to the gain controller or the limiter circuit widely.

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