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1. 发明专利

JP4846589B2 Synchronous transmission of audio and video data from the computer via the interface to the client 有权
公开(公告)号：JP4846589B2
公开(公告)日：2011-12-28
申请号：JP2006533742
申请日：2004-06-10
申请人：アップル・インコーポレーテッド
发明人：アンドリュー・ヤノウィズ , サミュエル・アール・ボウマン , ジェイムズ・エー・デルウィッチ , ジェフリー・シー・ディロン , ジョヴァンニ・エム・アグノリ , ジョン・オー・アブト
IPC分类号： G06F13/38 , G06F5/14 , G06F15/16 , G06F15/173 , H04N5/91 , H04N7/16
CPC分类号： H04N21/43632 , G06F3/14 , G09G2350/00 , G09G2370/025 , G09G2370/10 , H04L47/30 , H04N19/152 , H04N21/4113 , H04N21/64707
摘要： In an interface between a computer and a video client, a method for performing data transmission flow control, the method comprising: receiving a stream of input data from the video client according to a first format; converting the received input data to an output data according to a second format, the converting comprising generating one or more video data and one or more blanking intervals, the video data configured for display on the computer; and for each generated blanking interval, transmitting the output data from the interface, the transmitted output data enabling the computer to synchronize to the output data based on a rate of blanking interval reception.

2. 发明专利

JP2011018264A Data control circuit, device with the same, and data control method 审中-公开
标题翻译：数据控制电路，具有该数据的设备和数据控制方法
公开(公告)号：JP2011018264A
公开(公告)日：2011-01-27
申请号：JP2009163390
申请日：2009-07-10
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： MIZUTA MASAHIKO
IPC分类号： G06F13/38 , G06F5/14
摘要： PROBLEM TO BE SOLVED: To detect in advance that a buffer memory runs out of free space and to perform control for halting data generation, while allowing data generation to be easily restarted, since the buffer memory for holding data runs out of the free space and gets unable to hold data when data processing capacity of a host machine is less than the capacity of data input from a peripheral device.SOLUTION: In a data control circuit 1, a warning status flag 409 is enabled when the free space in the buffer memory 3 decreases to a predetermined level, and control is performed for halting input data loading, upon detecting that the warning status flag 409 is enabled, while restart information for restarting output of the input data is held.
摘要翻译：要解决的问题：为了容易地重新启动数据生成，预先检测缓冲存储器用尽可用空间并执行停止数据生成的控制，因为用于保存数据的缓冲存储器从可用空间中运行，并且当主机的数据处理能力小于从外围设备输入的数据的容量时，无法保存数据。解决方案：在数据控制电路1中，当缓冲存储器中的自由空间 3降低到预定水平，并且当检测到警告状态标志409被使能时，执行停止输入数据加载的控制，同时保持用于重新启动输入数据的输出的重新启动信息。

3. 发明专利

JP4446527B2 Scan converter and method parameter settings 有权
公开(公告)号：JP4446527B2
公开(公告)日：2010-04-07
申请号：JP30845599
申请日：1999-10-29
申请人：株式会社メガチップス
发明人：靖久丸毛
IPC分类号： G06F3/153 , G09G5/00 , G06F5/06 , G06F5/14 , G09G5/12 , G09G5/391 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of overflow and underflow when a small capacity line memory is used in place of a large capacity frame buffer. SOLUTION: When the number of actual output effective lines is larger than the number of theoretical output effective lines in the discrimination result of a discriminating circuit 50, it is judged that the reading speed from a line memory 45 is faster than a writing speed. When it is reversed, it is judged that the reading speed is slower than the writing speed. In accordance with the judgement above, a CPU 40 controls the starting time of the reading of a reading circuit 47 so that overflow and underflow are not generated in the memory 45. In the previous stage, errors in the reading and writing speeds are reduced in advance as much as possible on the basis of the discrimination result of the circuit 50.

4. 发明专利

JP2008288833A Information processing apparatus and method, and information processing system 有权
标题翻译：信息处理装置和方法以及信息处理系统
公开(公告)号：JP2008288833A
公开(公告)日：2008-11-27
申请号：JP2007131284
申请日：2007-05-17
申请人： Sony Corp , ソニー株式会社
发明人： FUKUHARA TAKAHIRO , HOSAKA KAZUHISA , SHIMURA KATSUJI , INAGAKI TSUGUNA , TAKAHASHI HIROO
IPC分类号： H04N5/225 , G06F5/14 , G06F13/38 , G06F13/42 , G11B20/10 , H04L12/70 , H04L12/823 , H04L12/835 , H04L12/875 , H04L13/08 , H04N19/00 , H04N19/102 , H04N19/134 , H04N19/152 , H04N19/196 , H04N19/59 , H04N19/63 , H04N19/89 , H04N19/895 , H04N19/91
CPC分类号： H04N5/232 , H04N5/23203 , H04N19/115 , H04N19/132 , H04N19/146 , H04N19/63 , H04N19/645 , H04N21/23406 , H04N21/2383 , H04N21/4382 , H04N21/44004 , H04N21/440254 , H04N21/6377 , H04N21/6379 , H04N21/643 , H04N21/64761 , H04N21/658
摘要： PROBLEM TO BE SOLVED: To easily suppress an increase in unnecessary delay time and to suppress unnecessary deterioration of quality as contents, with data transfer of contents. SOLUTION: When the number of precincts accumulated in a buffer exceeds a predetermined threshold, an output forbidding unit 285 performs bank-over control in response to notice from a number-of-precincts confirmation unit 284 to forbid output of encoded data of the precinct right after a precinct being currently output. The present invention is applicable to, for example, a digital triax system. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了容易地抑制不必要的延迟时间的增加并且通过内容的数据传送来抑制不必要的内容劣化。解决方案：当缓冲器中累积的区数超过预定阈值时，输出禁止单元285响应于来自区号确认单元284的通知而执行重写控制，以禁止编码数据的编码数据的输出目前正在输出区域之后的区域。本发明可应用于例如数字三角系统。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP3998314B2 First-in-first-out storage device 失效
公开(公告)号：JP3998314B2
公开(公告)日：2007-10-24
申请号：JP953198
申请日：1998-01-21
申请人：沖電気工業株式会社
发明人：英治湖本
IPC分类号： G11C7/00 , G06F5/12 , G06F5/14 , G11C8/04
CPC分类号： G06F5/12 , G06F5/14 , G06F2205/123 , G11C8/04
摘要： The first-in first-out storage device has a write counter for counting as a write address the number of data write operations of a write side circuit, a read counter for counting as a read address a number of data read operations of a read side circuit, a RAM which stores data input from the write side circuit into a storage region that corresponds to the write address when the write side circuit has performed the write operation and outputs the data stored in the storage region that corresponds to the read address to the read side circuit when the read side circuit has performed the read operation, a full-state detection unit which detects whether the write operation of the write side circuit needs to be restricted or not based on the write address and read address, a flip-flop which outputs a detection result obtained by the full-state detection unit to the write side circuit in synchronization with a write clock signal based on which the write side circuit operates, an empty-state detection unit which detects whether the read operation of the read side circuit needs to be restricted or not based on the write address and read address, and another flip-flop which outputs a detection result obtained by the empty-state detection unit to the read side circuit in synchronization with a write clock signal based on which the write side circuit operates.

6. 发明专利

JP3950178B2 The first-in, first-out buffer system 失效
公开(公告)号：JP3950178B2
公开(公告)日：2007-07-25
申请号：JP24784294
申请日：1994-10-13
申请人：株式会社大宇エレクトロニクスDaewoo Electronics Corporation
发明人：龍圭朴
IPC分类号： G11C7/00 , G06F5/14 , G06F5/16
CPC分类号： G06F5/16

7. 发明专利

JP3926524B2 Fifo storage device 有权
公开(公告)号：JP3926524B2
公开(公告)日：2007-06-06
申请号：JP31511299
申请日：1999-11-05
申请人：株式会社リコー
发明人：斉山本
IPC分类号： G06F5/06 , G06F5/14

8. 发明专利

JP3694339B2 For decoding system adaptive bit stream demultiplexing device 失效
公开(公告)号：JP3694339B2
公开(公告)日：2005-09-14
申请号：JP33881394
申请日：1994-12-28
申请人：株式会社大宇エレクトロニクス
发明人：根煥金
IPC分类号： G06F5/14 , H03M7/30 , H04N7/52 , G06F5/06
CPC分类号： H04N21/4341 , H04N21/4392

9. 发明专利

JP3598321B2 Buffering data exchanged between buses operating at different frequencies 有权
公开(公告)号：JP3598321B2
公开(公告)日：2004-12-08
申请号：JP2000518329
申请日：1998-10-27
申请人：エミュレックス・デザイン・アンド・マニュファクチュアリング・コーポレーション
发明人：スー，サム , ター，ダン , チャウ，ヴィ
IPC分类号： G06F13/12 , G06F5/14 , G06F13/36 , G06F13/38 , G06F13/40
CPC分类号： G06F13/4059

10. 发明专利

JP2004206220A Arbitrary waveform generation device 有权
公开(公告)号：JP2004206220A
公开(公告)日：2004-07-22
申请号：JP2002371814
申请日：2002-12-24
申请人： Yokogawa Electric Corp , 横河電機株式会社
发明人： KIMURA TAKAHIRO , YOSHIDA FUMIHIRO
IPC分类号： G01R31/3183 , G06F5/06 , G06F5/14
摘要： PROBLEM TO BE SOLVED: To realize an arbitrary waveform generation device capable of changing an output waveform by variably using operation clocks while using a DRAM for storing waveform data.
SOLUTION: The arbitrary waveform generation device is provided with a 1st size counter driven by a low speed clock, an address counter driven by a high speed clock to output an address, a waveform memory for outputting waveform data on the basis of an output from the address counter, a temporary storage part for inputting the waveform data from the waveform memory by the high speed clock and outputting the waveform data by the low speed clock, a 2nd size counter driven by the high speed clock, and a determination part for inputting a count value of the 2nd size counter and a count value of the 1st size counter and determining whether a difference value between both the count values is larger than a threshold or not. When the difference value is larger than the threshold as the determination result of the determination part, the operation of the address counter, the waveform memory and the 2nd counter is stopped and the writing operation of the temporary storage part is stopped.
COPYRIGHT: (C)2004,JPO&NCIPI

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