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    • 10. 发明专利
    • Memory controller, semiconductor memory device and decoding method
    • 存储器控制器,半导体存储器件和解码方法
    • JP2012244305A
    • 2012-12-10
    • JP2011110719
    • 2011-05-17
    • Toshiba Corp株式会社東芝
    • SAKAGAMI KENJIISHIKAWA TATSUYUKIKONDO KATSUHISATAKAYAMA ATSUSHI
    • H03M13/19G06F12/16
    • G06F11/1068G06F11/1048G11C29/00H03M13/1105H03M13/1111H03M13/1137H03M13/116H03M13/1177H03M13/1185H03M13/1188H03M13/45H03M13/6502H03M13/6505H03M13/6577
    • PROBLEM TO BE SOLVED: To provide a memory controller 3 that has a small packaged memory capacity and a small circuit scale.SOLUTION: The memory controller 3 configured to decode a unit frame of data encoded by LDPC coding through partially parallel processing based on a check matrix comprising a block that is a unit matrix and a plurality of blocks where each row of the unit matrix is sequentially shifted includes: a buffer 24 for storing threshold determination information about the data read out from a memory section 5; an LLR conversion section 16 for converting the threshold determination information to an LLR; an LMEM 12 for storing probability information β calculated during iteration processing of repeating column processing and row processing on the basis of the LLR in an iteration unit sized the same as or smaller than the block; and a CPU core 10 for transferring the probability information β stored in the LMEM 12 to the buffer 24 every time the iteration processing is completed in the iteration unit.
    • 要解决的问题:提供具有小的封装存储容量和小电路规模的存储器控​​制器3。 解决方案:存储器控制器3被配置为基于包括作为单位矩阵的块和多个块的校验矩阵来解码通过部分并行处理由LDPC编码编码的数据的单位帧,其中每行的单位矩阵 顺序移位包括:缓冲器24,用于存储关于从存储器部分5读出的数据的阈值判定信息; LLR转换部分16,用于将阈值确定信息转换成LLR; 用于存储在重复列处理和行处理的迭代处理期间基于迭代单元中的LLR计算的概率信息β的LMEM 12,其大小与块大小相同; 以及用于在迭代单元中每次迭代处理完成时将存储在LMEM12中的概率信息β传送到缓冲器24的CPU核心10。 版权所有(C)2013,JPO&INPIT