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    • 2. 发明专利
    • Differential output circuit
    • 差分输出电路
    • JP2013135314A
    • 2013-07-08
    • JP2011283952
    • 2011-12-26
    • Toshiba Corp株式会社東芝
    • KAMEDA SATOSHIAOYAMA TAKUMA
    • H03K19/0175H04L25/02
    • H03F3/45654H03F3/45183H03F3/45659H03F2203/45408H03F2203/45424H03F2203/45641H03F2203/45696H03F2203/45702H03F2203/45726H03K19/018528
    • PROBLEM TO BE SOLVED: To provide a differential output circuit that is applicable to both LVDS and CML schemes without any significant increase in circuit area.SOLUTION: The differential output circuit includes a current control circuit for, at a first setting, fixing a first variable current source at a certain value of impedance in controlling a current flow, and at a second setting, comparing a monitor voltage of a monitor node with a reference voltage and controlling the current flow through the first variable current source such that the monitor voltage becomes equal to the reference voltage. The differential output circuit includes a data signal control circuit for, at the first setting, controlling second and fourth MOS transistors on/off in response to second and fourth data signals while keeping first and third MOS transistors on, and at the second setting, controlling the first to fourth MOS transistors on/off in response to first to fourth data signals.
    • 要解决的问题:提供适用于LVDS和CML方案的差分输出电路,而不会显着增加电路面积。解决方案:差分输出电路包括电流控制电路,用于在第一设置下固定第一变量 电流源在控制电流时具有一定的阻抗值,并且在第二设置下,将监视节点的监视电压与参考电压进行比较,并且控制通过第一可变电流源的电流,使得监视电压变得相等 到参考电压。 差分输出电路包括数据信号控制电路,用于在第一设置下响应于第二和第四数据信号控制第二和第四MOS晶体管的导通/截止,同时保持第一和第三MOS晶体管导通,并且在第二设置下控制 响应于第一至第四数据信号,第一至第四MOS晶体管导通/截止。